JFE2140: JFE2140

Hey Steve, 

We have both a Pspice model and a Tina model available for download on the JFE2140 product page that can be found here:

https://www.ti.com/product/JFE2140#design-tools-simulation

We offer both Tina spice and Pspice for Ti as free downloads that can be found on the same link. You may be able to use the Pspice model.  

Best Regards, 

Chris Featherstone

Thanks Chris, that gets me almost there. The spice models won't open but was able to view the net-list in Altium.Seems like there's a diode between G and D but additionally there are three protection part X_U1, X_U2, X_U3 ESD_OUT_JFEx140. I'm interested because I need to know parasitic capacitances. Or can I just use the Cj0 of 0.1pF in each case used in D_D1 ? Also I see .model ESD_SW that appears not to be connected to the JFET. I tried looking in Tina too, all that shows is the FET when really I need to see the parasitic diodes/etc. Nay ideas ?

Hey Steve, 

I do not believe that we have data readily available for the protection diode parasitic capacitance. I would need some time to investigate. As the protection diodes within the JFE2140 are rather robust, I would assume a diode capacitance in the low pF-range, maybe 1...2pF. In any case the capacitance will also depend on the applied reverse voltage. 

We will look further into this to see if a better answer can be obtained. 

Best Regards, 

Chris Featherstone

Hi Steve, 

The protection diodes have approximately 1 pF of additional capacitance..  They are the same as what is used on the JFE150, we did measure the difference in CISS with the clamps added vs. no clamps.  I don't know what is attributing to the difference you are seeing, can you tell us more about how you are measuring it on your system?

Regards,
Mike

Thanks, I tried that and used TI's spice model for the JFET but still doesn't solve my problem. Circuit uses JF2140 in a TIA configuration with device connected to a LTC6228 pin 6 to in-, pin 2 to in + each with a 300 Ohm pull up to +5V via a common 50 Ohm resistor. . Sources are tied together and fed to -5V via a 510 Ohm resistor. Pin 3 tied to +5V, pin 7 to -5V, pin 4 to gnd.Feedback from LTC6228 is via two 6.8 K resistos in series paralleled withe two 1.5pF NPO capacitors each leg connected JFE2140 pin 8. Pin 8 also connected to photodiode 140pF to ground.

. On bench we are seeing rise/fall times of around 22nS with 10% overshoot then recovery, but simulation shows only 35nS rise/fall time. To get a match we either need to lower feedback capacitors to 0.5pF each, or add about 20pf Cgd on each FET in the JFE2140 hence y questions about capacitance. PCB layout has area under parts cleared of ground and even has ground guard-banding between 2140 pins. (calculated capacitance is negligible).

Clearly 1.5pF series feedback capacitors can't be as small as 0.7pF but 20pF Cgd for the 2140 of even stray on the board isn't feasible either so am somewhat puzzled. Hopefully you can figure the schematic from my description but if not feel free to send an email and I can send you a copy.

Hi Steve,

Sorry for the delay here.  Let me get your email, that would be easier to understand what you have here.  I'll reach out for a friend request to connect.

Regards,
Mike

Hi Mike, my email is steve@oainnovations.com. My client has used the JFE2140 as a TIA, when I measure the input capacitance I'm seeing several hundred pF capacitance with the JFE and a few low capacitance diodes being the only parts capable of doing this. PCB is cleared of ground plane plus hundreds of pF would require terrible layout to achieve. Including this capacitance in the LTSpice simulation I get simulation results that are a reasonable match to bench measurements hence my questions :)

Hi Steve,

Ok, I reached out over email, it would be helpful to see the actual schematic.  I'll continue the conversation over email.

Regards,
Mike