Other Parts Discussed in Thread: DAC3162,
Hello, engineers:
I would like to ask a question. I am designing a circuit using DAC3162 and THS3217. I notice that the datasheet for the THS3217 labeled the input common-mode voltage range for the D2S stage of the device as -1V to 3V. where the datasheet states:“The 3-V maximum common-mode range is intended to support DAC supplies up to 3.3 V, where the average output operating current pulls down from 3.3 V by the termination impedance from the supply. For instance, a 20-mA tail current DAC must level shift from a 3.3-V bias on the output resistors down to 3 V or lower. This DAC-to-THS3217 configuration requires at least a 300-mV dc level shift with half the tail current in each side, implying a 30-Ω load impedance to the supply on each side of the 20-mA reference current.”
Coincidentally the DAC3162 is supplied at 3.3V and configured with a tail current of 20mA in my design, which means I'm going to define the impedance matching of the THS3217's input stage to be 60 ohms or more to control the input common-mode voltage within the range. I note that this input common-mode voltage range (-1V to 3V) is confirmed with the D2S stage of the THS3217 device supplied at ±6V. Considering that the input common-mode voltage is related to the supply voltage, if I increase this supply to ±7.5V, will its input common-mode voltage range be able to continue to expand? Further, can this common mode voltage be capped above +3.05V for normal use with 50 ohm impedance matching?
