TLV3605: TLV3605 || Synchornisation

Hi Shine,

Could you elaborate on what you are trying to achieve by feeding a clock signal to the comparator? The comparators in our portfolio are "continuous-time" comparators. They do not need a clock signal in order to switch. In other words, the comparator is always reading the inputs and will switch accordingly. The nLE/HYST pin of the comparator is meant to be used to adjust the hysteresis of the comparator or to enable the latching function of the comparator. An example use case would be that TLV3605 is triggered and latches, then the FPGA detects the signal at the output of the comparator, does its appropriate action, then clears the latch for continued use.

Hi SIU,

The objective is to synchronise the LVDS output voltage from comparator with the clock of the FPGA so as to ensure that when the FPGA clock is used to sample the comparator output, it doesn't sample the output at an invalid LVDS voltage level. Let's say during the differential P & N cross over of the signal which could be a logic HIGH or LOW.

Like I mentioned, one of the comparator inputs is a random analog signal of frequencies of around 250MHz and the other input is a fixed reference voltage. This means, the output LVDS voltage from comparator can be random in nature. I was checking if the Latch pin of the comparator is fast enough to handle a clock signal of 300MHz from the FPGA so that every time, during a clock edge, the comparator produces an output and the same clock is used to sample the LVDS output voltage of the comparator. Please suggest an approach to achieving this even by using any other circuits.

Hi Shine,

Thanks for clarifying your goal. You won't be able to use a 300MHz clock signal to synchronize the TLV3605. A 300MHz clock signal implies a period of 3.33ns. The TLV3605 latch has a pin has a setup time of -3ns and a hold time of 6ns. This would mean that the random input would always transition in an invalid input transition region:

Exiting the latch mode also introduces a delay t_PL:

These two aspects introduce nonidealities that you will need to take into account if you want to input a clock signal into the latch pin of the comparator. 

From your response, it seems like you want to hold the output of the comparator stable such that the FPGA will not sample the output of the comparator at a transitional state. Is it an issue for the FPGA to sample at a transitional state? If the goal is to use the comparator as a 1-bit ADC that detects whenever the random input crosses the reference, the FPGA would still quantize the LVDS output of the comparator whether the output has settled to a valid LVDS level or not. Simply sampling the output of the comparator in unlatched mode would better reflect the random input signal since there are no transition requirements or added delay due to the comparator constantly entering and exiting the latch condition.

LMH7322 is a device with latch that has a lower setup and hold time than the TLV3605. This device may be better suited to a clock signal, but please read above to determine if synchronization of the comparator is needed at all.