Tool/software:
I have a microcontroller (AMD MicroBlaze SoC) polling the INA237 DIAG_ALERT register (address 0x0B) as part of a monitoring loop. When the CNVRF bit is high (signaling a conversion is ready) then a read of the conversion registers is initiated.
Very intermittently (approx. once per hour) during a read operation it appears the INA237 will ACK the read command during bit 8 of the address byte (R/W bit) instead of bit 9 (ACK bit). This pulls the SDA line low while the controller is attempting to drive SDA high to set the read bit.
The result of this behavior is the I2C controller hangs and stalls with the SCL idle. The INA237 then stalls with the SDA active (ACK) waiting for the SCL to transition low signifying the end of the ACK cycle. After 28 msec the INA237 releases the SDA line, effectively creating a STOP condition and releasing the bus back to idle.
The early ACK signal only appears during communication with the INA237. It always appears during the first read transaction after a write command to set the read register pointer. This pattern is not seen on any other I2C device in the system, leading us to suspect the INA237 as the cause. See the images below taken from a logic analyzer of the I2C bus for specifics:
Image 1: three good full read transactions followed by a good write for the next read register pointer, then a hang at the end of the address byte for the read operation.
Image 2: zoomed-in view of the error. Can see the brief HIGH pulse on the SDA line, as if the INA237 is attempting to perform an ACK reply during bit 8 instead of bit 9.
Image 3: zoomed-out view of error, where SDA is released 28 msec after the error putting the bus back to idle state.
