Part Number: JFE150
Other Parts Discussed in Thread: OPA202, TINA-TI, TPS7A94, , JFE2140

Tool/software:

Hello everyone, I am wokring with the JFE150 and I have a couple of questions about the Application Note from Chris Featherstone.

I tried to reformulate what is in the Application Note, to confirm or rectify the different equations and understanding about this Application Note. I wrote it all in a markdown file that I attached in this topic for everyone who wants to use/correct it too.

The following text is a copy/paste with adaptation of the markdown file. I used markdown because it is quite useful for mathematic equations (Latex). You can use any markdown editor, it should work fine. I attached the pdf with thsi topic too.

JFE150_ApplicationNote_analysis.zip

My understanding about the JFE150 application note:

Controller view and link to JFE150 circuit

To compute transfer function, bode plot and other analysis of this JFE150 Low Noise preamplifier circuit, we first transform and model this schematic to a well-known an non-inverter controller-view model.

To do that we first convert the circuit into a small-signal and T-model schematic. Then we assimilate the different parts of this new schematic to the non-inverter controller-view model and finally we calculate the different gain equations, transfer functions and so on.

Small Signal and T-model view explanations

We base our analysis on small-signal T model. Why do we then put all power supplies and input voltages to ground? And why is our JFET component equivalent to a current source in series with a resistance?

All power supplies and input signals to ground:

> Because we consider them as not moving, constant, and we want only to analyse the small variations. Which is equivalent to say that all power supplies or input sources are "NULL", or grounded in electronic

>[!QUESTION]
>Is this assumption correct?

JFET as a current source with a resistance in series:

> The JFET will be in Ohmic region in our working frequency an polarity, as we set a "fixed" voltage across its Grid and Source, it means that a current is "activated" and fluctuating inside it, this fluctuation is due to the tension set on its Gate. The Ohm's law implies that when there is a current and a voltage, there is also a resistance, which is the invert of the conductance $g_m$ of our JFET

>[!QUESTION]
>Is this assumption correct?

Final Small Signal T-model representation
Therefore, our system will look like that

figure 1: JFE150 schematic - small signal and T-model view

Overall gain computing

The circuit in figure 1 may be actually seen as a non-inverting topology, with a feed-forward gain A_{ol}, and a feed-back gain beta like this:

Figure 2: Controller view of a non-inverter topology

For this kind of controller view has the following overall closed-loop gain:

A_{cl} = A_{ol} / (1+A_{ol} . beta)

>[!INFO]
>The mathematics to reach this equation is not given in this document but may be done looking at TI precision Labs op-amp videos.

Assimilation of small signal schematic to non-inverter view:

The inverter view is composed of 3 elements:
- The substraction of feed-back signal to input signal.
- The feed-forward gain, or open-loop gain, which is generally high
- The $\large \beta$ network which is the gain of output signal ($\large V_{out}$), fed-back to input signal ($V_{in}$)

Assimilation of circuit in figure 1 into a controller-view model:

Figure 3: assimilation of JFe150 circuit to a controller view model.

With:
- Yellow box, the feed-forward/open-loop gain, composed of the current source g_m * V_{gs} and the operational amplifier opa202.
- Blue boy, the feedback gain $\large \beta$ made out from the resistances network.
- In red, the addition/substraction of input signal and feedback signal. It is made across the R_{gs} resistance and is the V_{gs} voltage

>[!INFO] Detailed explanations why we can represent it like that in the following chapters.

#### Substraction of feedback signal to input signal

In figure 1, the "lower" pin of of R_{gs} is actually the negative input of our add/substract circle. we can consider it like that because if we consider V_{in} not "moving", any voltage coming back from feedback loop over R_{f2} reduces the value of V_{gs}. Which in turns, reduces current gain of our T-model JFE150 i_{ds} = g_m * V_{gs}.

>[!QUESTION]
>Here I am confused because in figure 6.1 of JFE150's datasheet: *Drain-to-Source Current vs Gate-to-Source Voltage* as well as other curves of page 6. It looks that the lower V_{gs} is, the larger becomes the drain-to-source current i_{DS}.
>Or is it that the negative feedback will actually, (up until -1V) make V_{gs} more negative, and decrease drain-to-source current?
>There is also this DC bias current I_{DS} Am I confusing/mistaking the two here?

Feed-forward gain A_{ol}

The feed-forward or open-loop gain A_{ol} is the ratio of $\large V_{out}$ over the voltage coming into the yellow box. Which is actually the difference of V_{in} and V_{fb}, which is the voltage across R_{gs}: V_{gs}

Feed-forward gain: A_{ol} = (V_{out}) / (V_{gs})

As input impedance of OPA202 is considered as very high (not always the case for Bipolar based op-amp), all current flows through R1, therefore, V_{out} is the tension across R1

It means that V_{out} = R_1 . i , with i the current generated by the current source of our JFET. This current is defined by: i = g_m . V_{gs} we can the write:

V_{out} = R_1 . g_m . V_{gs} ->  V_{out} / (V_{gs}) = R_1 . g_m

So our feed-forward gain is:

A_{ol} = R_1 . g_m

>[!AFFIRMATION]
> Here we consider that current source and capacitors are perfect. Which means no intrinsic resistance of current source and C_D is a short. But then what about C_1? it should be then considered as a short too and shunting R_1

>[!QUESTION]
>Here I name the feed-forward gain as the "open-loop" gain of my inverting topology, on a controller view. Is it correct?

>[!QUESTION]
>I use only V_{gs} in the feed-forward gain. But is it not V_{gs} + V_{in}?

>[!QUESTION]
>On Tina-TI, how is it possible to compute the graphic trans-conductance over frequency? It is the figure 2-2 of JFe150 Application Note: *Ultra Low Noise preamplifier*

Feedback gain \beta network

The feedback gain is quite simple, as it is the usual voltage divided network. Therefore:

\beta = V_{fb} / V_{out}  = R_{S2} / ({R_{F2} + R_{S2})

>[!QUESTION]
>Here we consider C_S as a short in our working frequency, which means that R_{S2} // R_{S1} is approximately R_{S2} because R_{S2} << R_{S1}
>It means that capacitor C_S has to be correctly calibrated for our desired work frequency. Is it correct to make such an assumption?

Closed loop gain A_{cl}

Now that we made all the assimilation of our JFE150 circuit to a typical non-inverter controller model, we can compute the closed loop gain.

For A_{ol} \beta >> 1 (so for very large A_{ol}) we can simplify the equation:

What does it means to custom this design?

Closed loop gain $\large A_{cl}

For closed loop gain to be correct, the open-loop gain must remain very high compared to 1: A_{ol} . \beta >> 1
It means that at higher frequencies, as the open-loop gain becomes lower, this equation is not correct anymore and the closed loop gain follows the open-loop gain curve.

The open loop gain is dependent of trans-conductance value $\large g_m which itself depends on the Drain-to-Source current I_{DS}.

>[!QUESTION]
>There is in the application note, a diagram showing transconductance g_m over frequencies but none in JFE150's datasheet. How can I compute/get this curve?

Drain to Source current

We also need to be careful with I_{DS} current because it has impact on the input-referred voltage noise (Figure 6-11 of JFE150's datasheet).

>[!QUESTION]
>Here what is exactly the difference between DC drain-to-source current I_{DS} and the small current i_{ds}? How can I be careful when using JFE150's datasheet? It is actually not mentioned in datasheet.

Negative feedback loop

The value of V_{gs} substracted by the feedback voltage should not go below -1V or our circuit will be "open" and distortion will appear. it means that input signal V_{in} should not go beyond a certain value, as well as V_{fb} otherwise we work outside our possible voltage range.

>[!QUESTION]
>Is it correct to think this way? Could it actually lead to distortion in overall circuit and output curve?

Power supplies

The power supplies of the circuit should also be very clean not to degrade the voltage noise density.

>[!QUESTION]
>What could be here the best choices? Low-noise LDOs like the TPS7A94/96?

Thank you very much in advance for your answer and replies
Best regards
Jeremie