OPA197-Q1: Internal ideal circuit diagram of OPA197-Q1

Hello Marek,

Thanks for the response. Yes, in  my case Vss is grounded. But how does 1.8V reach Vss which is at ground potential ? Ideally all the voltage(2.5-0.7=1.8V) should drop across resistor Rs which is 6.8K in my case since cathode terminal of input clamping diode is at ground potential.

Any current thru the Rs resistor must flow through ESD diode.

Hello Marek,

Sorry I didnt understand. could you please elaborate ?

Manoj,

You did not provide me with details of your schematic and voltage you measure at different nodes so I can only assume certain things: any voltage drop across Rs is only possible when the current flow thru it - this means that the same current must also flow thru ESD diode. Therefore, voltage drop from 2.5V down to Vss is a sum of voltage drops across Rs and diode.

Hello Marek,

Here is the snapshot of TINA simulation file. when T3 base is low, I observe -1V at T1 collector and -0.5V at U1 output. Is this because of the ESD diodes on the output ?

Best Regards,

Manoj.

What I have from you is following:

Can you simulate your circuit condition by going to Analysis -> DC Analysis -> Calculate DC Condition and show other biasing nodal voltages like VF1, Vos and VM1?   Also, please attached your Tina-TI schematic so I may duplicate the issue.

Hello Marek,

Here is the TINA simulation file.

sboma36c.TSC

Best Regards,

Manoj.

Manoj,

Manoj,

Because of the large 438uA current thru R8 resistor, a non-inverting input terminal gets pulled down to -480mV turning on ESD diode to positive supply - this results in Vcc at -1.089V (see below).  A negative Vcc forward bias output ESD didoe pulling it down to -543mV.   At the same time Vcc forward-bias parasitic diodes of T1 transistor causing the current flow in opposite than normal direction - see red arrow of the current flow thru ESD and parasitic diodes. The total currents (AM6) of 564uA gets sunk by the negative supply to ground.

Manoj.TSC

Hi Marek,

Thanks for the explanation. However i still have couple of questions.

1. Could you please explain how Vcc node will have -1.089V ?

2. Is this circuit configuration causes any impact to the device performance in the long run ?

Best Regards,

Manoj. 

Manoj,

With Vcc floating and 2.5V input, OPA197 attempts to properly bias up that requires IQ of ~1mA.  This results in 2.98V drop across 6.8k resistor (480uA*6800ohm) and forward biasing of parasitic ESD_INP diode (additional 0.6V drop) driving Vcc to -1.089V (see current path below).  However, schematic below does NOT account for additional OPA197 internal parasitic junctions, which in actual application may result in different Vcc condition than the simulation below.

For this reason, you should NEVER allow Vcc to float as this condition may result in damage to IC.  Thus, in order to prevent said condition, you must add on the supply line a Transient Voltage Suppressor (TVS), which in case of Vcc floating will clamp the node a diode below ground preventing any damage to OPA197 - see below.

Hello Marek,

Thanks for the detailed explanation. But i still dont understand few things.

1. when we have a 2.5V input how come there is a 2.98V drop across R8 and R8 should limit the current to 367uA(=2.5/6.8K) in this case its 438uA.

2. How is the negative voltage is generated at Vcc when the input is positive ? is there a charge pump inside the device ?

Best Regards,

Manoj.