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TL331B: power on reset with high fail rate

Part Number: TL331B
Other Parts Discussed in Thread: TL331, LM339, TL331LV,

Tool/software:

Hi team,

customer see in a fail rate around 7% that they saw all the input and output pins are pull high together with VCC, which is not the expected waveform .

is this because we don't have Power on reset or you think it's not cause?

check  PU4403 in below  schematic 

TI TL331.pdf

  • Hello Fred,

    The TL331 family is under PCN for a die cahnge. The dies have different res[ponses to both inputs outside range.

    Please see sections 3 and 5.3 of the LM339 family appnote:

     Application Design Guidelines for LM339, LM393, TL331 Family Comparators

  • Hi  Paul,

    sorry, it's a little complicated to process, can I get a short conclusion since customer is quite urgent on this Fail return?

    also this is new design-in, so we need to notify customer if we need to change to solution with POR.

  • Hi Fred,

    customer see in a fail rate around 7% that they saw all the input and output pins are pull high together with VCC, which is not the expected waveform .

    What is your expected waveform during this power-on time? The oscilloscope image is showing that both inputs and VCC are changing, so it's hard to see what the device output of the device should be as PWR-OVPOP-VCC goes from 0 to 3.8V. Section 5.10 of the applications note that Paul posted describes start up behavior for B-die.

  • Hi Paul, SIU,

    I think I got it.

    they expected to see output low during power on actually,

    but the IN+ voltage is just a little bit lower than IN- when VCC is 0.55V. so I think this is a marginal design problem under large mass production.

    I just told them to  increase the cap value PC4413 to slow down the PWR_OVP-3(IN+) rise time, please correct me if this is not good solution.

    one last thing, customer found other competitor's block diagram  looks very alike as below,

    so they want to know if all these BJT comparator without POR will always have this power up state under VCC 2V?

    www.diodes.com/.../AS331.pdf 

  • Hi Fred,

    Increasing PC4413 will increase the charge time of the IN+ node, but this solution does not guarantee that IN- will always be higher than IN+ during power cycling. For example, if the power cycling of the system happens quickly, this larger capacitance in the IN+ node will take longer to discharge such that it may be higher than IN- once the power turns on again. It would be more reliable to use a device with integrated POR (like TL331LV) such that it will output a known state irrespective of the input conditions. Note that for most of our open-drain devices, the output is usually HI-Z during POR.

    It's hard to comment about the behavior of competitor devices. Even though the functional block diagrams are similar, there's no way to tell how different their internal design/layout looks, as well as the differences in the process the device was created. The most accurate way to tell would be to test the devices with the same input stimulus; I can't really say what their behavior on power up would be, since any comments I make would be speculation.

    I'll be closing this post as we've taken this offline.

    Regards,

    Ho

  • Hi HO,

    sorry, customer wonder why our output in below waveform still end up as low even the IN+ rise faster than IN- during 0.55V<VCC<2?

  • Hi Fred,

    I'll be continuing this offline through email.

  • Hi team,

    is the output sink current of TL331B large enough to ignore the sourcing current (3.3V/56kohm) from pull up 3.3V when VCC is still below 1V?

  • Hi Fred,

    We don't test for output sinking current below minimum supply as TI doesn't guarantee device operation outside of the recommended operating conditions.