Tool/software:
Hello TI,
I am simulating a piezo transducer with capacitance of 66 nF and 100 K connected to this front end amplifier made for very low noise performance. The simulation results are horribly wrong. could anyone please let me know what is wrong in my simulation. Also I would like to calculate CMRR of this circuit from 10 Hz to 20 KHz. Please let me know. I intend to use it with gain of 10.
Please let me know what is the issue?
Hi Sumeet,
My recommendation would be to significantly reduce the complexity of the circuit first for debug. All DC voltages within the circuit should be analyzed and valid before noise or AC analysis can be performed. There are a few issues with this circuit. Neither JFETs are operating in the linear operating range. You can see that the DC drain to source voltages show that the JFETs are operating in the triode region. Also the JFET on the right doesn't have a DC bias at the gate node. Capacitor C2 is DC blocking the bias voltage at the gate.
I wrote an application note for the JFE2140 with the feedback at the gate. In your circuit you have it at the source and I don't believe this will work. My app note covers the JFE2140EVM that I also built and tested. Do you need differential inputs? I don't believe you will be able to achieve differential inputs with two JFETs and also have closed loop gain simultaneously. I have another circuit that can achieve differential inputs in a closed loop circuit however it requires 4 JFETs.
Here is my app note that covers the circuit I built and tested for the JFE2140EVM:
Best Regards,
Chris Featherstone
Hello,
Here is the fully differential solution with closed loop gain
Tina Simulation:
Best Regards,
Chris Featherstone
