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AMC1300B-Q1: AMC1300B Immunity Question

Part Number: AMC1300B-Q1

Tool/software:

Hello Experts,

We are using AMC1300B for a circuit breaker trip unit design.

To decrease CM dV/dt assigned on AMC1300B, we add 2.2nF Y2 capacitor between primary and secondary.

We found when Y2 capacitor is placed underneath AMC1300B (on the opposite layer) or close to AMC1300B on the same layer or opposite layer, during 4kV EFT test between primary and secondary of AMC1300B,

The output of AMC1300B will be saturated (without EFT, the output is normal, within the linear operating range).

When Y2 capacitor is placed far away from AMC1300B (>2cm), no any abnormal at all.

Could you help explain what sensitivity of AMC1300B causes this phenomena? 

What is the recommended placement and layout between AMC1300B and Y type capacitors if Y capacitor is used?

Thanks in advance.

Best Regards,

Fenglian 

  • Hi Fenglian,

    Thank you for your question. This is the typical layout recommendation we provide in the data sheet:

    Placing the decoupling capacitors as close to the device as possible, placing the smaller capacitor closer to the device, and keeping either side capacitors symmetrical typically gets the best performance. 

    Could you provide a layout example of what garnered better or worse performance so we can evaluate better? Please let me know, thank you. 

    Best regards,

    Eva

  • Hi Eva,

    Many thanks for your reply.

    Here goes the layout, we have three channels, A, B, C.

    The test result shows B is bad, A is the best, C is in the middle.

    When these Ycaps for Channel B is moved to Top layer and away from AMC1300B, its output is again saturated during 4kV EFT test.

    I am afraid respecting the layout you shared is not enough.

    Then, I have questions on the recommended layout (such kind of layout recommendation can be found in TI's high speed digital isolators),

    Q1. why does the clearance area need to be kept? 

    Q2. what kind of disturbance is sensitive to AMC1300B, is it electric field or magnetic field? please help precise this so that we can apply the appropriate solution, for example, add magnetic shield or electric shield.

    Q3. are there some ways to remove the required clearance area?

    Thanks and Best Regards,

    Fenglian 

  • Hi Fenglian,

    If layout A is performing best, does that meet your system's requirements? If not, what does the output look like? Is the output only saturating during the test, or does it persist after the test?

    Please let me know, thank you.

    Best regards,

    Eva

  • Hi Eva, 

    Due to insulation constraints (8mm clearance, 12.6mm creepage is needed between primary and secondary of isolator), it is not possible to implement same layout as A for B and C, we need address it within the limited space. So, it is important to know what the root cause is behind the problem, and then take the applicable solution.

    The output is saturated only during the disturbance, once disturbance disappears, it quits from saturation and recovers back to normal operation state as before disturbance is injected.

    Did you experience such phenomena? 

    if so, could you share your findings and recommendations?

    if not, could you help perform similar tests to check this point?

    This kind of phenomena does not solely appears for this isolator, it may exist for the other digital isolators which using capacitive coupling and  OOK modulation with high frequency carrier), our other project teams (in France and India sites) met this issue recently.

    To accelerate solving this issue, is it possible to have a meeting call to exchange this topic efficiently together with the other project teams? 

    Thanks and Best Regards,

    Fenglian 

  • Hi Fenglian,

    We are looking into this. I will email you offline to work towards a resolution.

    Best regards,

    Eva