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BUF802: Sundry bias pins

Joselito Go
Expert 4910 points
Part Number: BUF802

Tool/software:

HI Experts,

For the BUF802, there are three bias pins R_bias, IN_Bias, and Aux_Bias.  for R_bias there are plots of the bandwidth versus two bias points, and a plot of bias current vs R_bias pin resistance (pg 18 of the datasheet).  The plot yields an equation of (7.83mA + 100(4.56/Rbias), and the bandwidth and IQ results are documented.

The voltage presented at IN_Bias and Aux_bias is not documented, so that a bias current can be calculated.  In addition there is no documentation on how to choose a bias current, if the voltages were known?

IN bias current and IN_Aux bias currents are presented in the datasheet, but are not bipolar but positive only.  Which direction is the current flowing for a positive bias current, into or out of the pin?

VOS, for IN, is presented in the datasheet, but is only negative.  Since VOS is modeled as in series with the input signal, what 'direction' is it in series with the input signal? That is, is the voltage presented to the amplifer higher (more positive) or lower, by the VOS amount, than the voltage present at the pin?

The functional block diagram in Figure 8.1, shows DC voltages between the CLL, CLH and the bases of the corresponding clamp transistors.  These DC voltages are not documented in the datasheet?

Regards,

Josel

  • 0
    TI__Expert 8530 points

    Hi Josel,

    The Aux bias pin is simply connected to VS- to enable using the Aux input. This is typically used for a composite loop configuration as shown in figure 8-12 in the datasheet.

    The IN_Bias pin is also used in the composite loop mode. It is typically just connected through a 10M Ohm resistor to the input pin which forms a high freqeuncy pole created by the input series capacitor and then the 10M Ohm resistor. Please again refer to the datasheet Figure 8-12 and section 8.4.2 part 2. "High Frequency Region".

    For the IN_bias and IN_Aux pins I will need to confirm the bias current polarity. It may be possible to be either polarity.

    For the VOS, the voltage presented to the amplifier will decrease by the VOS amount. For example a 0V input signal would typically result in a -600mV signal on the output.

    Figure 8.1 just shows an approximation of the circuitry and it is actually much more complex. There is no static DC voltage on the clamps that you need to be concerned with. The voltage set at the CLH and CLL pins will set the clamping voltage at the output. You can see an example in Figure 8-5.

    Best,

    Jacob

  • 0 in reply to Jacob Freet
    TI__Expert 4910 points

    Hi Jacob,

    Thank you for this. I will wait for your confirmation about the current flow.

    Regards,

    Josel