OPA858-Q1: OPA858-Q1

Hi Deepthi,

What supply voltage are using for the opamp?
If you are using Vs+=5V and Vs-=0V, then the DC operating point is not defined properly for the circuit. The output headroom is 1V below Vs+ and 1V above Vs-, which means your DC operating output voltage should be between 1-4V. In this case the input common mode voltage will also be very close to the boundary (typ=0 max=0.4 as per datasheet).

Also, the 36 mV value that you quoted above, how did you measure? 

To understand more about TIA circuit please try our new TIA Circuit Design Tool here: Analog circuit design studio, here you can select any opamp or use the suggest opamp feature to get suggestions on best opamp for your needs, also you can see the complete noise analysis, frequency + transient response plots, and many more features.

Regards
Aditya

my supply voltage range is +2.5 and -2.5 , and i am measuring the 36mV at output using oscilloscope , i followed data sheet feedback resistance values , than also i am getting some 18mV of voltage at inverting terminal of the opamp , ideally it have to be offset voltage . my feedback resistance is 453ohm and input resistance 60ohm

Hi Deepthi, can you please send the schematic or circuit diagram for all the 3 measurements that you took?

1) TIA with Rf=0

2) TIA with Rf=1M

3) Opamp with Rf and Rg as per datasheet

Regards,
Aditya

I  connected R9 and R2 and remaining else are disconnected in the feedback place in pcb also by zero ohm resistors , and giving nothing at the input implies at opamp pin number 3 i am not giving any input from triax connector( open circuit ) , just measuring the input with probes of oscilloscope , the input inverting terminal voltage is 0.36 V , same circuit for 1, 2, 3  for 3rd case i am giving input voltage  in bread board by connecting with series resistor on bread board with Rf anf Rg mentioned as per datasheet .

Hey Deepthi,

There are a few possibilities that I think might be causing this offset issue:

1. PCB leakage: A 4.2mm thick PCB can have significant surface and internal leakage paths, especially if its not clean or if the material has high moisture absorption. These tiny leakage can get amplified by 1M Rf resistor, leading to elevated offset. I would suggest to thoroughly clean the PCB with proper solution like IPA. Cleaning the PCB will also remove any conductive flux residue.
2. Oscillations: TIA can be prone to oscillations, especially when high feedback resistors without feedback capacitors are used. These oscillations can sometimes rectify and appear as DC offset. For check your output with high-bandwidth oscilloscopes, and look for any signs of oscillations or instability. If present you will need to add a small feedback capacitor (You can use our tool to compute the min Cf needed: Analog circuit design studio)

Please refer the datasheet and TIA Tool: Analog circuit design studio to understand more about TIA circuits.

Regards,
Aditya

I am designing a transimpedance amplifier (TIA) where the input current comes from another device and consists of pulse-like currents in the range of nA to µA. I have the following questions:

1. Junction Capacitance (Cpd):

   • In the simulation tool you mentioned, can I set Cpd to zero, or should I estimate and include a realistic value?
   • How does this affect the circuit's behavior when dealing with pulsed currents?

2. DC Operating Points:

   • If I account for capacitance in my PCB layout (e.g., stray and parasitic capacitance), can I still accurately check DC operating points, or will these capacitances interfere with the DC analysis?
   • What best practices should I follow to ensure my DC measurements in the range of operating are correct in this setup?

Hi,

1. You should include a realistic value for Cpd, as setting it to zero would lead to a overly idealized simulation, which may not match real-world behavior. Cpd typically arises from photodiode junction, OpAmp inverting input, and PCB layout parasitic caps. For high-speed applications (For eg. pulses with ns width), even small capacitances  (in pF range) can significantly affect stability and bandwidth. You can check it by changing the Cpd in the tool and looking at the corresponding change in bandwidth (and thus noise), rise time etc. 

2. Yes can still accurately check DC operating points, even if you account for capacitance in PCB layout, because in DC conditions capacitances are open circuit and thus you can ignore them.  For ensuring DC measurements in the range of operating are correct, please refer to datasheet where all the best practices are mentioned. For example to check if your DC output voltage of TIA is within the operating range of opamp, check the electrical chars for Vout where the output swing for a given supply voltage will be mentioned. 

Regards,
Aditya

Title:

Op-Amp Oscillating at 84 MHz Even with DC Input – Stability Issue?

Question:

I am using an op-amp in an inverting configuration with the following parameters:

• Gain: 15 V/V
• Rf: 15 kΩ, Rg: 1 kΩ
• Supply Voltages: 5V (V+) and 0V (V-)
• Vcm (Non-Inverting Terminal): 2V

Even when I apply DC voltages to the inverting terminal, I observe an 84 MHz sinusoidal oscillation at the output on the oscilloscope. Changing the DC input values does not affect this oscillation. When I apply an AC signal (e.g., 50 Hz to 100Khz sine wave), the output still remains at 84 MHz. This oscillation occurs even when no input is connected.

Troubleshooting attempts:

• Tried adding feedback capacitors based on TI’s stability calculator → No change.
• Connected a 50Ω and changing  series resistor at the output to dampen oscillations → No significant change.
• Ran an LTspice simulation with the same circuit, and I  didnt see thid behaviour.

Could this be due to op-amp instability, parasitics, or PCB layout issues? Should I change the op-amp? What else can I try to stop this oscillation?

Hi Deepthi,

I checked the stability of you circuit on TINA TI simulation software, and the circuit looks to be unstable without feedback capacitor and Rf=15k, Rg=2k (As per your LTSpice schematic).

As you can see above, the phase margin of the circuit is only 16.5 degrees, whereas 45 degrees is needed for minimum stability. But I have used +/- 2.5V as supply and not 5V, 0V.

With 5 and 0V I am getting such irregular response-

I am not exactly sure why this behavior is happening, probably the DC bias point is not set properly, let me get back to you on this.

Few points from my side:

1. Which EVM board are you using? If not TI's EVM, please verify from datasheet that you have adequate decoupling capacitors close to OpAmp's power pins, and follow other layout guidelines too.
2. Please try once with split supply +/- 2.5V and use Cf of at least 0.5pF. You can ground the non-inverting input.
3. What probe are you using for measurement? What is the probe capacitance?
4. Even if oscillations still persist, you can add a series R isolation of 50Ω and check again.

Regards
Aditya 

Thanks for the reply ,

1.I am using the OPA858-Q1 in a transimpedance amplifier (TIA) configuration on my custom PCB. I have followed all the PCB layout guidelines from the datasheet, including Decoupling: Used 0.1 µF capacitors at the power supply input. TIA Configuration: Included a feedback resistor and a feedback capacitor. Grounding: The non-inverting terminal is directly connected to ground. I am not using the EVM board; this is my own design. Attached is the layout image for reference.

and i tested on one more board with only this opamp again made small board particularly for this opamp there also i am facing same issue , attached the layout of small board 

2.I am using the OPA858-Q1 in a TIA configuration on a custom PCB with 0.2 pF feedback capacitance and proper decoupling, but my output oscillates regardless of input, even with a split supply.

3.Keysight N2843A ,500MHz 10Mohm,11pF 10:1 300V RMS LATI.

4. 50Ω isolation resistor i place and tried, but the output still oscillates; even changing the resistor to 1kΩ results in oscillations at a specific frequency.

can you please help me in this ,why i am getting osillating behaviour and in dc also i am not able to observe rightvalues at output.

and one more doubt is , in ltspice i am getting this ac response

Hi Deepthi,

It looks like this issue may be related to the overall PCB design rather than specific component values. For high-speed applications, it’s crucial to follow proper layout guidelines, including short feedback traces, good bypass/decoupling, and appropriate GND/ power plane cut-outs for multilayer boards. I’d recommend reviewing the High-Speed Amplifiers PCB Layout Guidelines for best practices.

Let me know if you have any further questions.

Best regards,
Aditya

 thanks for the reply 

I will go through the above guidelines , 

but why the pspice is giving such strange results when you just change supply inputs , why the normal circuit with inverting configuration as you mentioned in previous reply  simulation , is unstable Phase margin is less, same circuit in LT spice is giving good result(81degree phase margin) . why ?

opamp in inverting configuration is it unstable?

I ran stability simulations for the OPA858-Q1 in both PSpice and LTspice, but the results are inconsistent—phase margins are different, and the PSpice results seem strange. Could this indicate instability of opamp , or is there a reason for these discrepancies between simulators?

can you please help me out .

Hey Deepthi,

Will look into it and get back to you by tomorrow.

Regards,
Aditya

okay , thank you sir, looking back for your reply.

Hey,

From where did you get the LTSpice model for OPA858? Can you please share your PSpice and LTSpice simulation files if possible. 

Many SPICE tools use different internal models for the same device. For example, LTspice’s model for the OPA858-Q1 may be a more detailed or updated representation (or even provided directly by TI) than the one you’re using in PSpice. These differences can affect how internal compensation, parasitics, and frequency-dependent behaviors (like phase lag) are handled. As a result, LTspice might predict a healthy phase margin (e.g., 81°) while PSpice’s model—if it has, say, extra phase shifts built into its representation—can show a reduced phase margin.

Regarding the rail issue, some models are more sensitive to the way supply rails are referenced or how rail-related parasitics are handled. It’s possible that the PSpice opamp model is more sensitive to these supply conditions, which could artificially lower the phase margin in the simulation. In contrast, LTspice might have a built-in assumption or a more robust handling of supply rails that avoids this issue.

An opamp in an inverting configuration (when properly designed) is not inherently unstable. The differences you’re seeing are more likely due to differences in the simulation models, numerical methods, and default settings between PSpice and LTspice rather than an intrinsic problem with the OPA858-Q1.

Regards,
Aditya Gosavi

OPA858 OPAMP with simple inverting configuration with gain 7.5V/V and all PCB parasitic capacitances at the inverting input, non-inverting input, and output  are included. while simulating this circuit in LTspice and Pspice  i am getting phase margin of 14degrees , so its unstable right? how to make this system stable.

Hi Deepthi,

To make the system stable you can try:

• Add a feedback capacitor of 0.5-1 pF across R1, which will compensate for the cap at inverting input due to OpAmp and PCB parasitics. You can reduce the feedback cap if the system is still unstable. 
• Add an isolation resistor (Riso) at the output, in series with C2. Usually a load cap of 10fF should not make the OpAmp unstable, but you add an Riso of 10-50Ω if the first fix doesn't work.
• Some resources on how to stabilize OpAmp circuits:
  • https://www.ti.com/video/4080235259001
  • https://www.ti.com/video/series/precision-labs/ti-precision-labs-op-amps.html
• I simulated the same circuit in TINA TI, and I got a phase margin of ~16 degrees. After adding a Cf of 0.8pF, the circuit has a phase margin of ~45 degrees, and is stable. I have attached the screenshots and TINA schematic below for reference.
• without Cf
• with Cf added

OPA858 Inv Config Stability.TSC

Regards,

Aditya Gosavi

Op-Amp Circuit: DC Offset at Output Causing Saturation Issue

Hi everyone,

after doing all this stabiiity analysis in opamp also ,I'm facing an issue with my op-amp circuit where a DC offset at the output is limiting the available swing and causing saturation when I increase the input amplitude.

Circuit Details:

• Input Signal: Sine wave of some frequency
• Feedback Resistor (RfR_fRf​): 1.5MΩ
• Input Resistor (RinR_{in}Rin​): 100kΩ
• Parallel Feedback Capacitor: Added for stability
• DC at Inverting Input: 40mV
• DC at Output: 1.22V

Issue:

I am getting an amplified sine wave at the output with the same frequency as the input, but the DC offset at the output is limiting the swing. When I try to increase the input amplitude, the output saturates instead of providing the expected gain. so why am i getting dc offset at input , which is eventually amplifying and giving dc offset at output , which saturates the sine curve  in oscilloscope .

 so yellow color graph is input which i gave from function generator , green color graph is the output of teh opamp where the sc is 1.36 .. and please ignore blue color graph , and the circuit  layout diagram is attached  

can you please help me with this.

Hi Deepthi,

To keep this thread focused on the original topic, could you please open a new thread for unrelated/ new questions? That way, it’ll be easier for others to follow along and find relevant discussions.

Thanks!

Aditya