Other Parts Discussed in Thread: XTR305
Tool/software:
Hello,
I am currently dealing with the XTR305 chip and I am trying to find a good balance between the values of the Cc, C4 and Rc (designators from DS,Figure 40). The challenge is achieving a max. phase delay of -3 degrees at 300Hz for both I and V mode, while varying the Rload from 50 to 500 in I-mode. As of now by using the TINA simulations it seems that the values that I found either amplify the signal at higher frequencies for small load resistance in I mode or achieve a phase delay higher than 3 degrees at 300Hz in V mode. Is there a way to achieve a filtering behaviour while keeping the phase delay within the required limits? Gladly I can provide more details if needed. Thank you in advance.