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AMC1350: IDD1 versus VDD1 above and below UVLO

Jeff Melvin
Prodigy 180 points
Part Number: AMC1350
Other Parts Discussed in Thread: TINA-TI

Tool/software:

When using a charge pump to power the high-side VDD1, it is important to know the IDD1 characteristics.

In section 6.9 the broad definition "IDD1≤8.1mA @ 3.0V<VDD1<3.6V", and "IDD1≤9.3mA @ 4.5V<VDD1<5.5V" is provided, but a constant IDD1 with a varying VDD1 is unlikely and there is no information provided below VDD1=3.0V.

Figures 6-39 and 6-40 show the expected increase of IDD1 with VDD1, and with temperature, but these are not worst-case curves and they do not go below VDD1=3.0V.

Can you please provide the expected worst-case IDD1 versus VDD1 from 0.5V to 5.5V?

  • 0
    TI__Guru 55412 points

    Hi Jeff,

    Can you share a bit more about your application and schematic? 

    I suspect I may know that circuit you are planning to use as a bootstrap, not a charge pump and want to confirm. Are you going to use the supply from the gate driver? 

    I can check with the team to see if this is readily available, but it may not be since VDD1 below 3V is not specified. 

    While the curves do not show worst-case scenario, only typical, the maximum specifications in the datasheet do encompass these parameters. 

    For worst-case I think it is reasonable to "shift" the curve up to estimate how it would look at higher temperature vs VDD1 voltage, or down to estimate lower VDD1 voltage with respect to temperature. 

  • 0 in reply to Alexander Smith
    Prodigy 180 points

    Alexander,

    The circuit is indeed a charge pump, operating from a 70...300VAC AC Mains to power the AMC1350.  This is just an AC Monitor, and there is no gate driver, or other circuitry powered from the AC Mains, on this card.  Sorry, but I'm not allowed to share details...

    I can certainly shift the curves to represent worst-case, as you have suggested, but that will not provide information regarding the IDD1 draw while in UVLO.  I have tried to unravel the PSpice model, but I'm not sure if I can even do that, and if I could I'm not sure that addresses proper operation below 3V.  Maybe someone knows if the PSpice model is accurate below 3V and how it addresses IDD1 in that condition?

    My initial approach was to assume 1250Ω in parallel with 5.7mA from Vdd1 to GND1, but I'm confident the part will not be drawing 5.7mA while in UVLO.  The charge pump circuit simulates well when modeling IDD1 as 484Ω from VDD1 to GND1, but it won't pull the part out of UVLO at 70VAC when using the 1250Ω║5.7mA model.  I could characterize an actual part, but I wouldn't know how to adjust the results to represent a worst-case situation.

    Thanks for your help...

  • 0 in reply to Jeff Melvin
    TI__Guru 55412 points

    Hi Jeff,

    I was able to speak with the team about this and we do not have additional characterization data for IDD1 below 2.9V. 

    The PSPICE model is meant to demonstrate typical parameters, unfortunately I do not think it will be helpful for this. 

  • 0 in reply to Alexander Smith
    Prodigy 180 points

    I'm sorry, but I didn't realize Vdd1 behaved differently when Vdd2 is powered or not.  Rather than leave my old graph here and create a new post, I thought I'd edit this post so there's no confusion for others...

    You are correct about the model.  I ran it in TINA-TI with a triangle voltage source to VDD1 and a current sensor in series.  The VDD1 current is zero when ramping up until 2.7V and after ramping down below 2.6V.

    Here's what I measured on the bench with a part that came out of UVLO at Vdd1≥2.7V and went into UVLO at Vdd1≤2.6V.  (Vdd2 on) = 5.1V:

    I can modify my model to approximate this, multiplied by 130% for worst-case, to guarantee the part comes out of UVLO above 70VAC...

  • +1 in reply to Jeff Melvin
    TI__Guru 55412 points

    Hi Jeff,

    This is excellent work, thank you so much for the follow-up.