THS3491: Request for Review: Summing Amplifier + Active Buffer Design for Capacitative Load

Note: I noticed that I left the REF pin disconnected on the THS3491 and have tied it to VGND. I also tied PD to +2.5V instead of my nonexistent +2V net.

Hi Arjun,

Thank you for all the details you shared. Unfortunately, we are not able to access google drive on our network. Could you please share a zip file with all the relevant information and files you would like to share. I did read over your description of what you intend to run. One potential concern is the goal of outputting an 8MHz signal at 8Vpp. This will require more slew rate than the OPA891 is capable of and will almost certainly lead to some form of distortion at the output. We do have faster devices but was curious if there were any power supply requirements in your circuit to narrow down potential options.

Best regards,

Ignacio

Good Afternoon Ignacio,

Thanks for getting back to me! I've switched out the Google Drive for a .zip containing all required materials, including the picture of my schematic.

Thanks for alerting me to the OPA891 slew rate issue. Looking back at Figure 5-7 on the datasheet, I can see how there might be distortion issues above 5Vpp. My initial post was a bit misleading; AWG_1 sends in an 8MHz, 8Vpp signal which is divided in half by the termination resistors, thus becoming 4Vpp. So, it might be okay to use the OPA891 because the maximum swing at that stage of the circuit should be 4Vpp; the THS3491 after the OPA891 has a gain of 2 and that's where the 8Vpp signal would be generated.

If there's a faster VFA I should use, that's fine by me if it's not much harder to design for! I am under the impression (correct me if I'm wrong) that, the faster the opamp, the more critical the layout and decoupling becomes, so my choice of the OPA891 was guided by 'just fast enough' logic. But again, I'm not too experienced with these IC's, so if there's a faster VFA I should use, let me know! My only power requirement is to be able to power both opamps with +-12V. Overall power consumption isn't a concern as this will be used in a lab setting, so I can use as much power as I want (up to 1W).

I'm also under the impression that it's easier to design a summing stage with a VFA than with a CFA. Let me know if this is true or not; if I can do everything with one less opamp, that's great! I also might not need the OPA387 if the voltage divider's output can go straight to the summing stage, rather than being buffered by the OPA387 before the summing stage.

Thanks again,

-Arjun

Hi Arjun,

Thank you for attaching the zip file. Although the device has just enough large signal bandwidth, at 8MHz we would likely see some sort of attenuation at the output as it is reaching its large signal bandwidth limit. We always recommend designing a circuit with a decent amount of margin as process variations can result in ac performance specs to vary between devices. One device to consider is the OPA814 as a potential option if you can supply +-6V. This will have more than enough large signal bandwidth and will still have enough output range at the +-6V supplies. If you require +-12V, the OPA810 could also be another potential candidate as this has better slew rate performance. They both come in a SOIC D package like the OPA891. The same layout guidelines will apply to all three devices.

As for the choice of VFA versus CFA, either can be implemented in a summing circuit and should not be a problem if you would like to use just one THS3491 stage. As for the assistance with the LDO portion of the circuit, I was able to find crosses for these competitor LDOs. I recommend starting a separate thread with this TPS7A2525 cross and your thread will get directed to the LDO team and they can assist and offer the best solution.

Best Regards,

Ignacio

Good Afternoon Ignacio,

Thank you for your analysis! I want to keep the number of parts as low as possible. Therefore, if the THS3491 can act as the summing amplifier, I'd like to eliminate the VFA.

I've attached a new image to this message of the revised circuit, with (my attempt at) the new summing network for the THS3491. Again, each input should have a gain of -2, so if each input were -1V, the output would be 6V.

I am not sure if inverting, summing CFA's follow the same rules as a summing, inverting VFA. I also have the notion that the input impedance of the inverting input on a CFA is low -- does this mean I have to carefully design the impedance of the summing network? Please let me know if my configuration will act as I intend, and if you have corrections, please let me know!

Thank you for your time and expertise,

-Arjun

Hi Arjun,

I attached a TINA simulation with the THS3491 as well as an image of what you could implement. I adjusted the Rf resistor for the noise gain the device will be in as a summing amplifier and adjusted its Rgs accordingly. I also adjusted the termination resistance to match to 50 ohms. As far as the rules for a CFA in this type of circuit the same ideas will apply. Although a VFA has technically a high impedance input at in-, when you close the loop, you will get your virtual short and in an inverting circuit this will behave like a low impedance node. The same principles apply to a CFA as it maintains a virtual short across its inputs as well.

As far as the schematic there are a couple adjustments I would recommend. For the NC pin, although you can leave it floating, it would be worth setting this to ground. This will help with spreading the heat to a large plane, in this case ground. I would recommend adding 1uF capacitors to ground in addition to the 0.1uF capacitors. One other consideration would be to add a supply capacitor of 0.01uF between VS+ and VS-. This should help with HD2 performance and is something we implement in our EVMs. For the PD pin, it can be set to VS+. That way when your connecting pin 7 to +12V, you don't have to via a separate potential of +2.5V and you can just connect both pins to one potential. For resistor sizes we do always recommend the smallest option available as this will ensure we minimize parasitics. However, we also used 0805 in our THS3491EVM so I believe you should be fine with this choice.

sboman3.tsc

Best Regards,

Ignacio

Good Morning Ignacio,

Thank you so much for providing me with these design insights and with the TINA simulation. I'll check out the simulation today. I'll implement the changes to my components and will lay out my board! I'll plan for a 4-layer board with GND | Signal-Power | Signal-Power | GND stackup.

Best,

-Arjun

Hi Arjun,

I would look at the THS3491EVM as a reference for your layout. Our EVMs are the best references we can share as they highlight all the layout best practices we tell customers to implement. Below is the link to user's guide.

THS3491 EVM User's Guide

Best Regards,

Ignacio

Will do, thanks Ignacio!

Good Afternoon Ignacio,

I've made the first draft of my board layout, and have attached a zipped folder with pictures of the layout and stackup. I've done my best to follow the THS3491 eval board layout and stackup. I will use an 8-layer PCB as shown in the datasheet, with the same signals/power on each layer as the eval board.

My main question is if I interpreted Figure 2 and Figure 3 on the eval board PDF correctly. In those images, it seems to me that the filled in polygon is actually where the ground plane of that layer is cut out, right? I am making this assumption because the datasheet specifies that the ground plane should be cut out under the feedback path to minimize parasitic capacitance.

Accordingly, I've attached pictures of the most important part of the board (the THS3491 and the power delivery/decoupling), and have shown where I cut the ground plane out. I also added a 10,000 pF EMI capacitor to VS- as shown in the datasheet, and 80 Ohm @ 100 MHz ferrite beads in series with +VS and -VS at the entry points to the board.

Let me know if my layout is clear based on the files, and if I should make final adjustments and go ahead with ordering. Thanks for all of your help thus far -- I'm looking forward to finishing this PCB.

LIA_AB_Mk2_Layout.zip

Best,

-Arjun

Hi Arjun,

That is correct the filled-in regions are the cutout regions of those layers in the figures we highlight. I was able to look at the images. I did not see any major concerns with the layout. However, one suggestion would be to reduce the via sizes under the thermal pad and increase the number of vias under the thermal pad. This will help with thermal dissipation. Another consideration would be to separate the signal lines C and D more to limit any crosstalk effects that could come from these lines being parallel to each other. Seeing the feedback path in your design, it might be worth splitting the feedback resistance into two resistors that would equal the Rf value we want. The idea being this will mitigate board parasitic due to this long trace in your feedback path. One other suggestion would be to place the termination resistors on C and D closer to the Rg resistors so that you can terminate the signal line closer to the end of the path which should ideally help limit potential reflections. Overall, the layout follows our suggestions really well and should behave as expected.

Best Regards,

Ignacio

Good Evening Ignacio,

Thank you for all of your guidance! I'll implement those changes, put the board together, and update you with how it goes. Your help means a lot to me; I'm glad I went with Texas Instruments for this project.

Best,

-Arjun

Hi Arjun,

Glad to assist in your project, please reach out if something is not working in the lab portion of the design.

Best regards,

Ignacio

Good Morning Ignacio,

I wanted to thank you for your help again and let you know that the amplifier is functioning well! It wouldn't have been possible without your help and fast response time.

Square waves with a steep edge show a bit of overshoot (see the oscilloscope trace below -- the yellow trace is the signal being fed to the amplifier, and the purple trace is the signal after the isolation resistor. The signal was a 1 MHz, 10 Vpp square wave).

In any case, my application only involves sine waves with frequencies below 10 MHz, so I have plenty of bandwidth and slew rate for my application. I probably will create a final iteration of the board, so if you have suggestions on how to minimize the overshoot, let me know! For a final iteration, I could use 0603 or 0402 size components for the feedback network.

Best,

-Arjun

Hi Arjun,

I am glad it is working as expected. As far as helping overshoot, I would try increasing the Rf resistor (adjusting the other resistors accordingly) and see if that helps. It will reduce your bandwidth but should ultimately help with overshoot. I would also try adjusting your Riso and see if you see a difference. The adjustment to smaller components should technically help as your parasitics would decrease but I would first try the things I mentioned prior to spending the time to fix the board as it might not do as much as we hope.

Best Regards,

Ignacio