Other Parts Discussed in Thread: SN65LVDS049,
Tool/software:
Dear Specialists,
I am having a problem in a circuit that i designed for electrical standard conversion, to be driven with a digital signal of 100 MHz.
This circuit is composed by two stages: The first stage is a SN65LVDS049 which convert from a LVCOMS33 into an LVDS (single ended to differential, and the chip can reach up to 400 Mbps).
This LVDS signal then enters the second stage, composed by the fully differential amplifier THS4511 with a 1.6*10^9 GBP.
All the schematic can be seen in the attached image, and also the related layout.
I chose the resistors Rf, Rg and Rt (respectively R9,R14 - R8,R12 - R11) following the document https://www.ti.com/lit/an/sloa054e/sloa054e.pdf?ts=1740446605799 starting from the Chapter 10.
The desired gain was 1.57.
Unfortunately the gain was larger than 1.57 (it's about 3) and the complete circuit doesn't work at 100 MHz, but works only at frequencies much lower thant 100 MHz, like 100 kHz.
Furthermore, i have misured with the oscilloscope at the LVCMOS input of the SN65LVDS049 and there the signal is already messed up, as if the second stage loads a lot the first one.
Have I made some gross mistakes that I can't see? I'm a digital designer and i'm not expert in the analog field.
I appreciate your great help in advance.
Best regards,
Alessandro

