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OPA695: component failure / PCB improvement

Part Number: OPA695

Tool/software:

Hi,

I am working on a new PCB version using the OPA695IDBVR and I would like some PCB advises. 
Generally on my current design the amplifier stage is working wellI but when my design has troubles it is always due to an OPA695 failure.
I have no idea why it is like that and I would like to solve it in my new PCB version.

I use the OPA695 as an inverting amplifier, our standard resistor couple is 402R / 200R for an amplification of 2. We sometime increase the amplification up to 6 with a couple 402R/68R. 
The signal to amplify is between 200MHz - 1GHz.

I use a non balance power supply. +8V / -3V. Could it be a source of problem? I have readen some element about that.

I have a 4 layers PCB and the PCB design has no polygon cutout on the different layers under the component. It also has no cutout for pins IN+ / IN- / OUTPUT. Is it ok for you?

I plan to add cutout on all the layers under the component. Do you think it is a good idea to trace the feedback net under the pin? Do you recommend me to go throught vias to connect the feedback resistor to the output?

Thank you in advance for your help,

Best regards

  • Hello Gautier,

    I have a few follow-up questions, but I am able to help you here.

    First, I want to ask what your input signal details are for this application?

    Second, what is your desired output signal?

    For a selected gain, there is a recommendation for OPA695 for the corresponding RF (feedback resistor) selection: this curve is found on p. 31 on Figure 7-2.  For a gain of -2 V/V, the Rf value is 499 Ohms.  I would expect this value to decrease a bit for G = -6V/V, between G=-8V/V (Rf = 442 Ohms) and G=-4V/V (Rf = 475 Ohms).

    I believe the resistor selection of Rf = 402 Ohms is not optimal for your desired inverting gains; Rf = 402 was specifically selected for G = +8V/V.

    I also recommend section 7.4 (p. 40-41) for guidelines on high-speed layout.  We strongly recommend power & ground plane cutouts under the input network and feedback network of the OPA695.  Your provided changes are what I would consider the minimum necessary layout change.  As you are working with a 200MHz - 1GHz signal, you will want to check proper input/output termination and if you need controlled-impedance traces.  We often use controlled 50-Ohm impedance traces and select improved dielectrics for PCB manufacturing (better dielectric constant than FR4).

    An unbalanced split supply power scheme is okay if you understand the trade-offs and limitations, the OPA695 has certain headroom requirements for input and output swing on split supplies.  

    Please ask additional questions and make use of the support my team and I can provide here.  If you need to go offline or share design files via email, I can provide an email contact to you through the e2e forum message service.  You can connect with me on e2e to message privately.

    Best,

    Alec

  • Hi,

    Thank you for your quick reply.

    It is a signal coming from a TIA stage, the signal is inverted on that stage. We are using a capacitor to remove the DC part before the amplifier stage.

    My desire output signal is a low SNR and the best amplification possible.

    Ok if I understand well it is clearly better to make evolve both amplifier resistors. I didn't take care about this figure thank you for the sharing, I will make them evolve in couple and not only change the IN- resistor.

    After your answer I will add the feedback resistor in my cutout. I have added a 50R trace for signals. Interesting point about material improvement I will study it.
    About my feedback track management I'm not sure to get your point.
    Is it better to be under the chip?

    Or on the BOT face which means 2 vias on the track?

    I am not the instigator of that split power supply. I don't think that it is a good way to do in our setup but now I'm stuck, change will have a huge design impact.
    2 problematics seem important for me in my usecase, noise is higher and our amplified signal can't go up to +3V.
    Do you see another point that I should take care about unbalanced power supply in my situation?

    We can continue this subject in public but I would also discussed some other technical points with you in private. Thank you for your proposal.

    Best regards,
    Gautier

  • Hello Gautier,

    Let me check on best practice for routing feedback trace.  In general vias add inductance which may have an adverse effect especially at these higher frequencies. 

    I will check for any private messages from you. 

    Best,

    Alec

  • Hello Gautier,

    Do you have an update or any additional support needs?  I hope your design has progressed and you were able to determine which improvements and changes need to be included in a PCB revision?

    Best,

    Alec