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Original question:

PGA280: What is the minimum and maximum time delay between falling edge SCLK and falling edge ECS_N output on GPIO?

PGA280: CP0 value to cause ECS_N to fall after SCLK falling edge?

Lauren Mayfield
Expert 7985 points
Part Number: PGA280


Tool/software:

I am following up from this E2E thread: https://e2e.ti.com/support/amplifiers-group/amplifiers/f/amplifiers-forum/1470875/pga280-what-is-the-minimum-and-maximum-time-delay-between-falling-edge-sclk-and-falling-edge-ecs_n-output-on-gpio

It's my customer asking these questions.

The PGA280 specification (SBOS487B-JUNE 2009-REVISED MARCH 2020, pg 24) indicates that CP0 =1 causes ECS_N to fall after the SCLK negative or falling edge (from section 7.4.1.1). The app note you linked in the previous post indicates that that CP0 =0 causes ECS_N to fall after the SCLK negative or falling edge (Figure 5).

Which document is correct? My customer wants to use the SCLK falling edge so should CPO be set to 0 or 1?

 Also, figure 5 of the Application Note has the ECS_N set to be asserted on the rising edge of the SCLK. Do we have a better plot for the ECS_N that shows more accurate Tpd between the falling edge of SCLK and the assertion of ECS_N?

  • 0
    TI__Mastermind 22312 points

    Hello Lauren, 

    Thanks for pointing out the confusing nomenclature, I will update the document. 
    I always believe scope captures more than I do drawings and words as one is real data and everything else can have human error, so if we compare: 

    I drew 1 byte command, 8 clock pulses with clock polarity on the negative edge of the clock: 

    CP = 0 asserts ECS after the positive SCLK (as denoted by the dashed line) and as is described in the datasheet (SBOS487B): 

    Therefore, I will update the wording in this document PGA280 Communication via SPI™ 

    from: "With bit CP0 (clock polarity) set to '0', the ECS falls on the negative edge of the clock. If SP0 is set to '1' (in Register 2), it would fall with the previous rising edge."

    to: "With bit CP0 (clock polarity) set to '0', the ECS falls on the after the next positive clock. If CP0 is set to '1' (in Register 2), it would fall with the previous negative clock edge." 

    With my previous context, I realize my previous response doesn't make sense. I will reference this post in that one. 

    We do not have a more zoomed in version of the Tpd timing between CLK and /ECS signal but it can be assumed to be very small (almost immediate). 

    All the best,
    Carolina