TLV27L1: Wild current consumption spread at Lower Vdd

Hi Raymand,

Thanks for your reply.

Allow me to explain more clearly, the circuit takes in 4-20mA current, and the output voltage is fixed by downstream circuit (R30,R31 divider and U4 Vref), also the downstream circuit will use and sink all the unused current into M2,R29. Due to series resistance R33 between the circuit and the downstream circuit, the op-amp V_U1 will be 7.4~8.0V depending on the supplied current Isrc, where Iout = Isrc - Icircuit, and V_U1= 7.41V + Iout * 33

It has been tested with R3 bypassed, and the Vin+ reference supplied by precision benchtop power supply (meaning REF3012 circuit can be ignored), that the circuit consume 10uA more at low input Isrc=4mA compared to Isrc=20mA. Refer data in table below. This is part 1 of the mystery we are trying to understand, if the reduction is caused by op-amp design, as Iq/consumption usually increase with higher supply voltage.

For completeness, besides these operating conditions where the Vout always swing to max (comparator operation), there is another operating point where V_U1 is high enough that Vin- approaches 1.25V and op-amp starts regulating Vout.

Do you think the comparator operation can cause unwanted/undefined behaviors described on this page? - https://www.analog.com/en/resources/technical-articles/maximum-supply-current-that-wasnt.html.

Part 2 of the question is, that the higher consumption at 4mA input Isrc varies from part to part, and registered 35~80uA when tested at Isrc=4mA, and lower and smaller range (10~40uA) at Isrc=20mA. We confirmed by swapping op-amps between two boards that the current consumption follows the op-amp .The guess now for the different consumption of different parts is part variations but it is too much different that datasheet's max 11uA Iq value.

Unfortunately we cannot use TLV07 due to lower power requirement, appreciate the suggestion.

Regards,

SoonYet

Hi SoonYet, 

Soon Yet Chan said:

This is part 1 of the mystery we are trying to understand, if the reduction is caused by op-amp design, as Iq/consumption usually increase with higher supply voltage.

I think that you may have to look at different way. The input power for two current sources are different. I will take a look at the Isrc current source, where the V-I efficiency to generate 4mA vs. 20mA is different. You may have to look at the problem from power efficiency point of view, where Isrc may be operating at different operating point, where generating 20mA is more efficient than generating 4mA in your current source. 

You have to compare the two current sources with the same load, otherwise, it is difficult to figure out the issues. 

Soon Yet Chan said:

Part 2 of the question is, that the higher consumption at 4mA input Isrc varies from part to part, and registered 35~80uA when tested at Isrc=4mA, and lower and smaller range (10~40uA) at Isrc=20mA.

The circuit is basically driven from your current source 4mA and 20mA after Isrc. So this is I to V converter and driving 10ohm load. All the load power comes from Isrc at the current source based on the schematic. 

The pmos in the following circuit if near off, and majority of voltage drop will be across M2's source and drain. Do you know what is load power at 10ohm between 4mA vs. 20mA conditions?  Power_in = Power_out, so all the power dissipation at the right has to be equal to power_in which is calculated in the first diagram. 

If you have other questions, please let me know. 

Best,

Raymond