Tool/software:
Hi can you possibly let me know the expected capacitance between the feedback and inverting input (pins 2 & 3) of this part? I am using it as a TIA and at higher trans-impedance levels it will effect bandwidth.
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Tool/software:
Hi can you possibly let me know the expected capacitance between the feedback and inverting input (pins 2 & 3) of this part? I am using it as a TIA and at higher trans-impedance levels it will effect bandwidth.
Hi Steve,
I was able to ask the team, and we can roughly estimate that there is around 50 to 100fF of parasitic capacitance between these pins.
Best Regards,
Ignacio
Thanks Ignatio, Is this capacitance included in your spice model for the part, or do I need to add it to the model externally ?
Hi Steve,
No this is not something that is typically modeled. Input capacitance is the only capacitance that I can think of that sis included in most if not all of our models. Any other capacitance such as board or package parasitics are not captured in the model.
Best Regards,
Ignacio
Thanks Ignatio,that explain, that explains the extra 0.05pF approximately an extra between simulation model and board.