• State Resolved
  • Replies 12 replies
  • Answers 4 answers
  • Subscribers 48 subscribers
  • Views 246 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

OPA2171: [package]checking

Allen Lu
Intellectual 2300 points
Part Number: OPA2171

Tool/software:

hi   team，

 customer want to know the tolerance of 0.65mm pitch and1.27mm pitch as below.

 do we have some info to confirm the pitch range here? tks for the checking.

 

  • 0
    TI__Prodigy 340 points

    Hi Allen,

    Let me look further into this and I will get back to you.

    Thank you,

    Carrie

  • 0
    TI__Prodigy 340 points

    Hi Allen,

    The numbers highlighted below show the tolerance. Thus, the tolerance for the SOIC package is 0.010in and the tolerance for the VSSOP package is 0.008in.

    Thank you,
    Carrie 

  • 0 in reply to Carrie Stoll
    TI__Intellectual 2300 points

    Hi Carrie，

     Tks for the comments here.

     it seems the 0.65mm pitch will have ±0.13mm tolerance? so  the max = 0.65+0.13mm  pitch and min  = 0.65 - 0.13mm pitch?

    what`s the meaning of CAB near to the 0.13 M?

  • 0 in reply to Allen Lu
    TI__Prodigy 340 points

    Hi Allen,

    Yes, that is correct. The C,A, and B is referring to the specific measurement of the mechanical drawing. For example, "B" is referring to the width of the device.

    Best regards,
    Carrie

  • 0 in reply to Carrie Stoll
    TI__Intellectual 2300 points

    Hi Carrie,

     but we can see the A have 2.9~3.1 range and B same too.

     the C show 0.1 typ but no tolerance.

    it is weird that the 3.1-2.9 not = 0.13, and C 0.1 > 0.13, can you explain more? tks here

  • 0 in reply to Allen Lu
    TI__Mastermind 24320 points

    Hi Allen, 

    This question would be easily answered by our packaging team. For this reason I am looking for a contact for you internally that could answer packaging related questions. 

    Best Regards, 
    Chris Featherstone

  • 0 in reply to Chris Featherstone
    TI__Intellectual 2300 points

    Hi Carrie,

     can you help to loop packing team to help comments here?

  • 0 in reply to Allen Lu
    TI__Guru 70561 points

    Hi Allen, 

    Let me see if I can find and transfer you to the packaging team. Please give us a day or so. 

    Best,

    Raymond 

  • 0 in reply to Raymond Zhang1
    TI__Guru 70561 points

    Hi Allen, 

    Carrie is OoO. Sorry for the delay. 

    Allen Lu said:
    it is weird that the 3.1-2.9 not = 0.13, and C 0.1 > 0.13, can you explain more? tks here

    The following marking indicates the mechanical datum control for the pin tolerance. Anyway, I have to look it up, and the pins' tolerances are specified in the drawing (I have to use GD&T terminology). 

    If you have additional question, please show the drawing to a mechanical engineer who will tell you what these markings mean.

    If you have other questions, please let me know. 

    Best,

    Raymond 

  • 0 in reply to Raymond Zhang1
    TI__Intellectual 2300 points

    hi Raymond,

     tks for this new explanation, but the customer who is CQE only,  is not a  mechanical engineer ,so them still not clear to know how to reflect to the mm tolerance.

     is there a clear calculator language to reflect  the tolerance of 0.65mm here? i think a formula to show how to calculate it will be perfect.

  • 0 in reply to Allen Lu
    TI__Guru 70561 points

    Hi Allen, 

    We will confirm the calculation with our mechanical engineer and let you know for certain. From the drawing, thelead frame spacing estimation is the following. 

    If you have other questions, please let me know. 

    Best,

    Raymond

  • +1 in reply to Raymond Zhang1
    TI__Prodigy 340 points

    Hi Allen,

    Please see below for the packaging engineer's response regarding lead pitch tolerance.

    The tolerance for the leads of SOIC and VSSOP will differ due to their size, lead pitch, and overall design differences.

    In general, the lead tolerance for VSSOP is more stringent than SOIC because VSSOP is a smaller, more densely packed package with a tighter lead pitch.

    Please refer to the chart below.

    　

    SOIC

     VSSOP

    Lead pitch

    1.27mm

    0.65mm

    0.5mm

    Lead width (depends on the lead pitch)

    About 0.35mm - 0.51mm

    About 0.17mm - 0.27mm

    Lead width tolerance

    0.25mm

    0.13mm

    0.08mm

    Origin of the document

    JEDEC MO-059

    JEDEC MO-187

    The above are general ranges and typical values. The specific SOIC or VSSOP components produced by different semiconductor manufacturers may have slightly different lead sizes and tolerances. JEDEC MO-059 and MO-187 are public documents, and are available for download from the JEDEC website.

    Best regards,
    Carrie