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LM193: Maximum reverse current value and withstand time

Colin Chen
Intellectual 825 points
Part Number: LM193
Other Parts Discussed in Thread: LM339, LM393

Tool/software:

Dear Experts,

We are evaluating the operational amplifier LM193DR and would like to know the maximum reverse current that the chip can withstand in the event of negative input. Is this the IIk value(-50mA) in the reference specification? At this current, how long can the chip withstand without failure? Do you have any data to provide? Thank you~

  • 0
    Guru 316690 points

    Yes, IIK specifies the limit for the input clamping current. Also see footnote (1): "Exposure to absolute-maximum-rated conditions for extended periods can affect device reliability."

  • 0
    TI__Guru**** 164846 points

    Hello Collin,

    Because -50mA is possible, imagine how safe -1mA would be. It should easy to get down to this current.

  • 0 in reply to Ron Michallick
    Intellectual 825 points

    Dears,

    Thank you for your response.

    Are LM193DR and TL331QDBVRQ1 chips still old designs at present? Do the internal ports not have ESD protection as shown in the following figure? Is this ESD protection structure only available on models with version B? Thank you

  • 0 in reply to Colin Chen
    TI__Guru**** 164846 points

    Colin,

    Colin Chen said:
    Are LM193DR and TL331QDBVRQ1 chips still old designs at present?

    Not all, see PCN section of this application note: [APP] Design Guidelines for Devices with LM339/LM393 Cores

    The older design had no ESD specific (only purpose is ESD, does not preform any comparator circuit function) structures. Old design ESD protection came from larger components, transistors and resistors.

  • 0
    TI__Guru 60306 points

    Hello Colin,

    Although -50mA will not cause *damage*, we cannot say that the comparator will function properly during that time. The output, on any channel, may be incorrect while the current is flowing.

    At 50mA, the parasitic junctions are active. These junctions can "talk" to each other through the substrate, even into other channels.

    As Ron said, we would recommend keeping any fault currents below 1mA or less.

  • 0 in reply to Paul Grohe
    Intellectual 825 points

    Hi Paul,

    I have reviewed the application documentation provided by Ron and am still a bit confused. I saw the parameter IIK in the LM193 data manual, as shown in the figure below. Can it be explained that the internal input pins of LM193 are equipped with ESD?

    Also, is the input schematic in section 6.2 of the application manual for version B devices or for all LM339 series chips with Ji3 and TiB processes? Have ESD been added to the input side for both processes？

    Thank you

  • 0 in reply to Colin Chen
    TI__Guru**** 164846 points

    Colin,

    Nearly every integrated circuit we sold throughout many decades has a diode from pins to negative supply because most IC have a common (shared) P doped substrate. A pin that connects to a N doped component completes this diode. So negative current neither proves or disproves an ESD cell.

  • 0 in reply to Colin Chen
    TI__Guru 60306 points

    Hello Colin,

    The original "Classic" LM393 family did NOT have a dedicated ESD cell - just the "body" diode that Ron described. The ESD "robustness" was just a result of the larger device sizes in the older process.

    The "B" and PCN'ed Ji3 or TiB  non-B devices now have a dedicated ESD cell on the inputs.

    Body diodes and ESD cells are not really designed for continuous current at Abs Max level (cant get the heat out), so we recommend to keeping the current to a minimum (<1mA best).