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TLV1851-Q1: Input leakage when supply is 0V

Matt Guibord
Genius 17340 points
Part Number: TLV1851-Q1

Tool/software:

I just want to confirm that the input leakage with 0V supply will be ~55nA when IN+/- are at a positive voltage. Essentially, same behavior as seen in the 1.8V supply plot (Figure 6-9) in the datasheet, but with the current "step" shifted to 0V. While it seems to be implied, my customer is looking for a more explicit understanding.

Secondly, am I understanding correctly that the ESD structure will prevent the supply from rising due to input leakage when the supply impedance is high-Z? Or essentially, the leakage current will flow through the V- pin only.

Thanks,
Matthew Guibord

  • +1
    TI__Guru 60406 points

    Hello Matthew,

    When the input is above the supply, the input source voltage above the supply actually provides the tail current for the input stage (the 55nA bias current). That is why the bias current rises into the nA's when above the supply voltage.

    But because it is not powered, the internal current mirrors will not be functional, so the input looks like a "dead" reverse biased junction, so the 55nA has nowhere to go. The current should be sub-nA at room temperature when Vs = 0V.

    The ESD diodes will clamp negative like a diode, but they will NOT clamp on the positive side. There is no clamp to V+. So any voltage applied to the input pin needs to be externally clamped to <40V.