INA239: INA239 ADC converter MISO always tri-state

Section 7.5.1.1 describes the required SPI signals. Please show a logic analyzer or oscilloscope trace of these signals.

Hi Vlad,

I agree with Clemens. It would be good to see a scope shot of the signals.

Best,

Holly

Uploaded : the first is a complete SPI frame reading the device ID , MISO and MOSI data decoded.

The second is the closeup of the first byte (register address and "read" bit) showing the timing in relation to CLK pulses. Shifting data at the rising edge of CLK, sensing at the falling edge. 

Received MISO data shows '0's but in fact it is a tri-state - I later pulled up that line with 10k resistor. As you see the CS is active ( '0') , it suppose to activate MISO but when pulled up with resistor MISO is always '1' (on the shotscreens the MISO is not pulled up whence shows 0)

Please let me know what am I missing to check.

I have to note that these forms I probed not directly at INA239 pins but on the other side of galvanic isolator from it because the master MCU and ADC chip are sitting on the isolated rails and I can't connect all the probes to the chip. But I checked one-by-one signals on the ADC chip side and confirmed that all signals reach the INA239 pins as you see here. And the chip is fed well +5V 

Figure 7-7 shows that the MOSI signal should be zero while reading the register value. (I doubt that this makes a difference, but try anyway.)

Prior to this run I had MOSI outputting all 0's after "read" command - it was the same. I think once the chip receives a "read" command addr[0] = '1' then what is shifted out by master is ignored.

As DT says " On an SPI read operation, the INA239 returns the data read
in the same SPI frame." which means after the 1st address byte with "read" command received, then remaining MOSI data within this frame is ignored.

Hi Vlad,

Have you verified that you meet the timing requirements as specified in section 6.6 - 6.7 of the DS?

all times can be seen on those two oscilloscope screenshots. Time scale is on the bottom. I did not find anything wrong but I can't vow I checked all the specs... Do you see anything suspicious ?

The timing looks OK.

The MOSI signals appears to be weakly pulled up during the read (it does not reach 5 V, and is noisy). How does it look on the other side of the isolator? Is it floating? Can you at least trace CLK and MOSI together on the INA239's side?

These are all push-pull lines on the MCU side  3.3V CMOS. I can't attach probes to the INA239 side of isolator. But I managed to touch single individual pins just to verify if these line well propagate through the isolator - they are fine, logic on INA side is 5V .

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Aside from this topic, It is very upsetting that TI chose to package this chip only in VSSOP with 05.mm step between pins. It is NOT a prototype-friendly. All new chips we first try in our made prototypes which are not auto-assembled by pick-and-place machine (how many businesses have their own pick-and-place machine?). I believe so is the R&D development in most businesses. VSSOP with 0.5mm step ( and so any ball- packages) is only for a mass production but any products must start from prototyping during development. We usually skip considering any new chip which is not prototype-friendly. INA238 and INA239 are the exception to our rule as these are so good we couldn't find alternatives... seems to be a mistake... we can't even visually check it under microscope - too small gaps between pins....days lost

We started development of a replacement for it - a pair of INA301 current shunt amplifier + ADC122S101 . Both are in VSSOP package but a bit larger 0.65mm step between pins. These are easier to prototype and claim much faster both a conversion and over-current alarm triggering.

I would highly recommend TI to give a little thought to their product packaging. Any new product starts from prototyping, not from production. For most companies the fastest way to prototype new chip in their own product is to quickly make a new PCB in-house. Which is  a manual work for the most makers. Package must be friendly for that. Any SMD package with 0.65mm step is still OK for that (though 0.95mm is better). Too small step deem such chip not worth the hardship. Trying the ready-made demo board is not a replacement for the user's own test PCB. It is better for the chip manufacturer to offer prototype-friendly packaging than investing in a demo board.

Hi Vlad,

Sorry to hear that it is giving you so much trouble. We offer EVMs as a means to help with evaluation and to avoid the painful soldering that has to be done like you said. The EVM is not a direct replacement for a user's pcb but it can be a helpful starting point in working out the kinks in a new system.

We would be happy to send you an EVM to help get to the root cause of this issue. Please let me know.

Best,

Holly

Thank you Holly for this offer but this will not help at this stage. I know the anticipated data exchange between INA239 and MCU. I have enough experience with properly working INA238 in my board ( I am still puzzled about how did we succeed to solder that board with 0.2mm space between pins !?!, I was surprised that it worked)... had lost enough days though... I am designing a schematic / PCB to replace this chip...

Please  let your management know about this IC packaging problem - this surely effects your bottom line... if TI wants to save money offering only a single package for IC , then let it be SMD package with  0.65mm between pins - a good compromise - this chip is not much larger than 0.5mm step yet it can be manually prototyped by experienced technicians and this is also a good small package for a mass production...