DRV104 Duty Cycle

Hi Andrew,

We do not have information about what exactly happens when the Vpwm voltage exceeds the 3.589V, 90% duty cycle condition listed in the data-sheet's Table IV. The comparator function shown in Figure 9 suggests the once the applied voltage exceeds 3.9V the comparator output would stay at a fixed level and the duty cycle would be 100%, but that is likely a simplified diagram and the actual operation may be different. Another  is the graph in Figure 7 shows the duty cycle error increasing as the applied voltage increases beyond about 3.5V. Therefore, it may be that the duty cycle does increase beyond 90%, but its error becomes larger and larger, and the duty cycle doesn't quite reach 100%.

Do you need the duty cycle to exceed 90%, or actually be 100% in your application? If having the answer about the DRV104 behavior when Vpwm is above 3.589V is important in your application we can set up the device and make some measurements. I would need to know the circuit configuration details so that the results would be directly applicable to your application.  

Please note that the holiday season is here and any measurements may not get completed until January.

Regards, Thomas

PA - Linear Applications Engineering

The reason I asked is because I have an analog PID controller driving the Vpwm pin and the opamp can drive all the way to the 5V rail if the system is given an unattainable setpoint, which is very likely due offsets, variances from compenent to compenent, part tolerances, etc.  The problem is that the device the DRV104 is driving is rated for 9V and my supply rail is 12V, thus my concern with a 100% duty cycle.

Hello Andrew,

I had a chance to set up the DRV104 on the bench and observed its behavior as the voltage applied to the duty cycle pin (V_PWM) was varied beyond the data-sheet limits. For the particular DRV104 device I measured the following:

• V_PWM = 3.591V  (maximum specified) - The duty cycle was approximately 88.6%.
• V_PWM = 3.600V (9mV overdrive) - The duty cycle remained at approximately 88.6%.
• V_PWM = 3.650V (60mV overdrive) - The duty cyle increased to about 93.2%.
• V_PWM = 3.700V - 3.800V (110mV to 210 mV overdrive) - The duty cycle increased and remained max'ed out at about 96.4%.
• V_PWM = or > 3.850V - The duty cycle snapped to 100%.

The duty cycle is maintained at 100% through V_PWM= 5V which is the maximum voltage level I tested. No appreciable increase in input current was observed at the 5V input level. Also, I did check the low-end and a level below about 1.150V resulted in a 0% duty cycle. The duty cycle is definitely less accurate once the V_PWM is moved outside the range listed in data-sheet Table IV.

Thus, it appears simplified comparator circuit shown in Figure 8 is correct. Once the ~3.9V threshold is exceeded the output remains in a state that forces the 100% duty cycle.

Regards, Thomas

PA - Linear Applications Engineering

Thanks for looking into this.

I guess I'll add a resistor divider to the output of the op amp to limit the Vpwm voltage.  I'll just need to take into account the current from 2.75*Iref and with 1% resistors I should get a pretty solid duty cycle limit.  It looks like Iref is dependent on Rfreq (Iref = 1.25/Rfreq).

Thanks again