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TAS2505: TAS2505 Sample Frequence 22.05Khz, 16bit

Xiaoxiang Liu
Expert 7575 points
Part Number: TAS2505

Tool/software:

Hi team,

Customer is using TAS2505. If the sampling rate is 22.05 kHz and the bit depth is 16 bits, how should the audio MCLK and BCLK be set? Can you provide the corresponding PLL register settings?

Thanks

Xiaoxiang

  • 0
    TI__Genius 10305 points

    Hey Xiaoxiang,

    BCK= FSYNC * number of channels * number of bits per channel. 

    Right now, the customer is able to calculate the BCK frequency based on FSYNC = 22.05KHz and number of bits per channel = 16 bits.The number of channels would be based on the i2s signal the customer is feeding into IC. All these values would determine the BCLK. MCLK isn't needed in these types of situations. PLL in this IC is usually in an auto-detecting mode. There is also the option of on-chip pll the chip provides. 

    Regards,

    Ore.

  • 0 in reply to Ore Ogundana
    TI__Expert 7575 points

    Hi Ore,

    The TAS2505 requires setting up the PLL, could you provide the corresponding register configuration?

    I'm not sure if the PLL is auto-detecting, the reference app-note provides some common configurations.

    Could you provide the PLL settings (PLLP, PLLT, PLLJ, PLLD, MDAC, NDAC, DORS) for the case of 22.05KHz and 16-bit?

    Thanks

    Xiaoxiang

  • 0 in reply to Xiaoxiang Liu
    TI__Genius 10305 points

    Hey Xiaoxiang, 

    First use the A2 instructions to select BCLK as your input

    Can you clarify in the thread how many channels you are using ? Also please clarify is the bit depth 16bit out of a wider word width ? for example 16 bit depth in 24 or 32 word width ? please clarify that as well.

    Once done, I could guide you through a hack on how to select values in table 3-16 to get a working PLL tree.

    If not response is given, I'll consider the thread closed.

    Regards,

    Ore.

  • 0 in reply to Ore Ogundana
    TI__Expert 7575 points

    Hi Ore,

    Thanks for your support. 

    Our customer is attempting to configure. If there are any issues, I will consult you again.

    Thanks

    Xiaoxiang

  • 0 in reply to Xiaoxiang Liu
    TI__Expert 7575 points

    Hi Ore,

    Our customer has made multiple attempts but still has some questions. Can you provide a case example? I have obtained some configurations:  I2S , 16BIT depth, SAMPLE: 48KHZ, SCLK: 1.536MHZ. How should our TAS2505-Q1 be configured?

    Thanks

    Xiaoxiang

  • 0 in reply to Xiaoxiang Liu
    TI__Guru** 109825 points

    HI Xiaoxiang,

    You may download AIC GUI from here: SLAC366 GUI for evaluation module (EVM) | TI.com

    This can be used to calculate PLL settings.
    Follow these instructions, for your specified example:

    1. Open CodecControl
    2. File -> New EVM Simulation ->Select any AIC device (do not select DAC device)
    3. Click on Digital Audio Processing block
    4. Click on Internal Clock Gen Module
    5. At the new window, input the required values
      1. Input Frequency = 1536000 Hz
      2. Sample Rate = 48000 Hz
    6. Use the first or any of the other results for PLL settings, make sure to also use the values for NDAC, MDAC and DOSR.

    Let me konw if you have any questions.

    Best regards,
    -Ivan Salazar
    Applications Engineer

  • 0 in reply to Ivan Salazar
    TI__Expert 7575 points

    Hi Ivan,

    Thanks for your support.

    Can we use only BCLK if MCLK is not available? I've noticed some audio playback anomalies with the customer, including sharp sounds, while some audio plays normally. I believe this is related to different sampling rates of the audio. The customer has some audio with a 48kHz sampling rate and some with an 18kHz sampling rate, but the customer reports that using the Aplay-Dplug parameters for playback will resample the audio.

    Thanks

    Xiaoxiang

  • +1 in reply to Xiaoxiang Liu
    TI__Guru** 109825 points

    HI Xiaoxiang,

    Yes MCLK can be left floating and use BCLK as long as the BCLK frequency and Sample Rate requirements are compatible. BCLK frequency too low may not be usable.

    You must verify that BCLK and WCLK signal frequencies are not changing for the different audio tracks. If these clocks change then a PLL settings would most likely have to change as well.

    Best regards,
    -Ivan Salazar
    Applications Engineer

  • +1 in reply to Ivan Salazar
    TI__Expert 7575 points

    Hi Ivan,

    Thanks for your support.

    Thanks

    Xiaoxiang

  • 0 in reply to Xiaoxiang Liu
    TI__Expert 7575 points

    Hi Ivan,

    This issue have been solved.

    We update the PLL parameter, and we found their SOC-converted audio has distortion.

    Thanks again.

    Thanks

    Xiaoxiang