TLV1H103-SEP: Comparator output issue in PSpice simulation when VEE is biased above GND

Hi Alexandre,

I have some idea as to what's causing this issue. Please give me some time to investigate and provide a fix.

Hi Alexandre,

I didn't create this model, so I tried to take a look at this model's hierarchical model to get more insight. Unfortunately, I couldn't find the hierarchical model our internal database, so I tried to debug this model through reading the flattened netlist. I believe this issue is caused by an issue in the input range block and latch block.

To give some context about our comparator models in general, an output of VCC/2 (mid-supply) is used to indicate error conditions in simulation. For example, if the inputs of the comparator are outside of the input common mode voltage range, the output will go to mid-supply in simulation to indicate an error. This will not happen in a physical device as the mid-supply condition is something we add in simulation; physical comparators will go to output high or output low.

Alexandre Bezier said:

Is this behavior expected in simulation?

With the conditions of VCC = 6V, VEE = 1V, VEE - 0.3V < (IN+, IN-, nLE/HYST) < VCC + 0.3V, I would expect the simulation to be functional and the output to switch and swing from 6V and 1V. This is because that is a valid operating condition. The comparator only "sees" the supply differential of 5V (VCC - VEE), which is within the recommended supply voltage.

Alexandre Bezier said:

Or is there a limitation in the SPICE model that assumes VEE must be connected to absolute GND?

This seems to be the case; there are blocks internal to the model that is referenced to the absolute GND (0) while some are referenced to the VEE pin of the comparator. This may be why changing the VEE to a non-zero voltage causes an issue in the operation of the comparator.

I have to note that you need to be careful when using a physical comparator in a "floating comparator configuration." Power sequencing is critical in this application. If you plan on using VCC = 6V and VEE = 1V, both VCC and VEE must "rise" together to avoid damage to the device. For example, if VCC rises from 0V to 6V while VEE stays at 0V, the comparator will be at its absolute maximum supply voltage for some time and damage may occur.

Thank you very much for your detailed and helpful response.

Just to follow up: is there any way to modify something in the SPICE model to make it work in a floating configuration.

I understand that the internal model might have certain ground assumptions, but if there’s any workaround (even at the subcircuit level), I’d be very interested in trying it.

Thanks again for your support!

Hi Alexandre,

Most of our comparator models are unencrypted, so you can make modifications through changing the tlv1h103-sep.lib included in the .zip file for the PSpice model.

Turn on the "All" option in data collection in the "Edit simulation profile" so that PSpice will save the internal nodes (since you'll be unable to descend into the model's hierarchy):

I made some alterations on my end to try to get it to work, but there was an issue with the LATCH subcircuit that is causing some glitches in my sims. I'll take a deeper look into it to see if I can rewrite the block.

Hi Alexandre,

An update on my end. I wasn't able to implement any quick fix to the model. It seems like I'll need to rewrite the latch block as well as make other alterations to the INPUTRANGE subcircuit. Since there is quite a modeling backlog at the moment, I can't really give an estimate as to when the fix will be implemented. I apologize for the inconvenience.

Hi Siu,

Thanks for the update. I understand that these kinds of changes can take time, especially with the current modeling backlog. Please just keep me posted once you have a better idea of the timeline.

Best regards,
Alexandre

Hi Alexandre,

I'll keep you posted with any updates through replies onto this post.

Thanks for your understanding,

Ho