This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS61178: Schematic Review and PCB implementation with TPA3116D2 Amplifier

Part Number: TPS61178
Other Parts Discussed in Thread: TPA3116D2

Tool/software:

 Class D Amplifier.pdfHello, I am looking for an overall schematic and potentially a PCB review (although the PCB is not complete and I am a total beginner when it comes to schematic and PCB production), specifically ensuring proper implementation and component values of the TPS611781. My overall project is an ESP32-controlled bluetooth speaker. For the project, I am powering the circuit with a 3S2P configured lithium ion battery pack producing about 12V. However, to get louder performance out of the TPA3116D2, I wanted to boost the voltage to around 20V. To do this, I decided to use the TPS611781 as its switching frequency can be configured well above the frequency range of the audio spectrum, and does not require many extra parts. I am not sure however that I chose correct values for components, so I would like that checked. Finally, I was wondering how grounds should be layed out on my PCB. I saw on the datasheet that power ground and analog ground should be connected only at one point, so I decided to have a copper layer on the top and bottom layer for analog ground which provides ground for the TPA3116 amplifier and some pins of the TPS611781 as outlined from the datasheet, and then another copper layer for power ground of the TPS611781 on the top and bottom layer. Finally, I included a net-tie to connect the grounds at a single point, but I wanted to know how I should actually make that connection on my PCB. Thanks for any help.

  • Oh I forgot to mention, but I was also wondering if the TPS611781 will be able to handle my power requirements. In a previous thread, another TI engineer said my small speakers would draw a total of about 2.6 A RMS, which should be totally okay with the TPS611781 according to the datasheet; however, it seems like the pin footprints of the chip are quite small and maybe not able to handle all of the current. But I am a complete beginner in PCB layout, so I could be totally wrong.

  • Hi Ronak,

    Thanks for using e2e.

    It is ok to support 20V/2.6A condition for TPS611781.

    For the schematic, please refer to the 9.2.4.4 Loop Stability and Compensation in datasheet to design the COMP pin parameters, it looks like not very proper.

    For the layout, please refer to the figure.36 in datasheet, basically I have these suggestion

    1.It looks like the AGND and PGND are not separate correctly, the FB, COMP, LIMIT and some other signal I/O should be connected to AGND instead of PGND,

    2.and  please increase the width of the power line like VOUT SW GND, they are too thin on your current layout.

    3.we recommend to use direct connection (left) instead of cross connection (right) on power pad for better thermal performance.

      

    Let me know if you have question.

    Regards,

    Nathan

  • Thank you for your suggestions on the PCB layout. I am having a bit of trouble following the math for the loop stability and compensation section. I tried the Webench tool and got Rcomp = 365kΩ and Ccomp = 380pF. Do these values seem more correct?

  • I think the Webench may not consider the 2x470uF electric capacitor on the PVCC, considering these two big capacitor, I think Rcomp should be 200kohm and Ccomp should be 10nF, this make more sense.

    Also a parallel capacitor on the COMP pin is required as shown below, the value of the Cp is related to the ESR of the 470uF electric capacitor, please check the datasheet of the capacitor and get the value based on the equation 31 in datasheet.

      

    Regards,

    Nathan

  • Thank you for the response. In the calculations, did you use Rout as 4Ω (just curious how that calculation works)? Also using two 470µF capacitors with an ESR of 0.05Ω each, would I use Resr as 0.05Ω (Cp ~ 220pF) or Resr as 0.025Ω (Cp ~ 110pF)?

  • Hi Ronak,

    The Rout is the load resistor of Boost instead of the amplifier, considering the output voltage of Boost is 20V, and maximum current is 2.6A, the Rout should be 20 / 2.6 = ~7.7ohm, and the ESR here should be 0.025ohm.

    Regards,

    Nathan.

  • Thank you, that makes sense. Another question I have in regards to layout. The schematic in the datasheet has components like Rfreq, Rlimit, Rc, Cc, etc. connected to AGND, but in the layout diagram, they seem to be more connected to PGND. I understand there's a net tie between AGND and PGND on the chip, but what should I do here?

  • I ended up doing traces like this. The grounds of things like Rlimit, Rfreq, etc. are connected to the board AGND, and PGND has its own plane, which is connected via a net tie to the AGND at the AGND pin. I tried to follow the example layout, so hopefully this is mostly correct.

  • Hi Ronak,

    Those component  like Rfreq, Rlimit, Rc should be connected to AGND, the layout looks ok now.

    The only one more suggestion is that we recommend to place one via next to the VCC capacitor's ground pad and one via close to AGND pin, so that these two net can be connected as short as possible by bottom layer.

    Regards,

    Nathan 

  • Thank you very much for your help!