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BUF802: Clamping circuitry

Randy Openshaw
Intellectual 2721 points
Part Number: BUF802

Tool/software:

Hi team,

I have a customer currently looking at using the BUF802 clamping circuitry and running into some issues. Do you have a more precise diagram or explanation of how the input and output clamping circuit works?

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The current circuit I have implemented is identical to the evaluation board composite loop however since we want to have the output of the BUF802 sit at 2.5V, I am applying -2.5V as shown in the diagram: 

Now I want to set my output clamps to clamp at 3.5V and 1.5V (+/- 1V away from the 2.5V CM). When I set the CLH to 3.3V it seems to clamp at 3.5V like I want it to, however I cannot get the CLL to work at all, I would expect that I just set the voltage at CLL to somewhere around 1.5V to get it to clamp there but I'm finding out that it doesn't work, I actually have to push the CLL voltage way higher, like in the 3V range to start seeing any clamping. My rails are set to -4V to 9V so that my mid supply is at 2.5V. So the voltage at CLL is actually passed the max input spec of the datasheet which said not to go higher than mid supply. Any idea on what I'm doing wrong? 

Best regards,

Randy

  • 0
    TI__Expert 3936 points

    The clamping voltage on the CLL side mainly depends on what voltage the RLOAD is tied to.

    In the case where they are evaluating using the BUF802 evm, I would recommend they tie the RLOAD in the measurement to 2.5V instead of GND or 0V. This should help fix the CLL behavior on the sinking side.

    In the actual use case, I am assuming the following stage DC bias is closer to 2.5V instead of 0V which is why I am assuming they want to bias the BUF802 output closer to 2.5V.