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LMP7704-SP: SEE Report and reducing SEL vulnerability

Frank Wangberg
Prodigy 30 points
Part Number: LMP7704-SP
Other Parts Discussed in Thread: STRIKE

Tool/software:

I'm seeking clarification on a statement within SNOAA62B LMP7704-SP SEE Report (Rev. B), where section 7.3 mentions "SEL vulnerability increases for supply voltages in excess of 5.2V. Circuits using supply voltages at or below this level were not observed to experience SEL."

To clarify: were the circuits tested below 5.2V supply using any of the SEL prevention techniques listed in 7.3? And does SEL vulnerability exist in applications where supply voltage is above 5.2V despite SEL prevention techniques being used?

Thank you,

  • 0
    TI__Guru* 76401 points

    Hi Frank, 

    Frank Wangberg said:
    were the circuits tested below 5.2V supply using any of the SEL prevention techniques listed in 7.3? And does SEL vulnerability exist in applications where supply voltage is above 5.2V despite SEL prevention techniques being used?

    Yes, the LM7704-SP SEE report is found that, during a heavy-ion strike in Space application, the ESD clamp inside of the op amp can momentarily turn on and short the supply pin. If large and low ESR capacitors were used, the bypass capacitor charge can dump through the clamp, resulted in very large and fast transient current (EIPD events). This can happen (if Vs > 5.2Vdc) on low impedance power rail (LDO, battery or switchers).

    No reported issues were observed if the Vs ≤ 5.2Vdc is used in Space application (in SEL/SET context). So the SEE report recommends to use 10nF NP0/C0G capacitor, and isolate larger bypass capacitor (>220nF) with series 5Ω next to the Vcc pin, see the layout suggestion in Figure 7-6 (This creates a pole at approx. 32kHz and limiting the transient current through the series 5Ω resistor). 

    The SEE report shows that there is residual SEL vulnerability, if Vs > 5.2Vdc,, even when some mitigation are used. 

    If you have other questions, please let us know. 

    Best,

    Raymond

  • 0 in reply to Raymond Zhang1
    Prodigy 30 points

    Hi Raymond,

    Thanks for answering, I think that resolves the first question: in greater context of section 7, it appears that for supply voltages less than or equal to 5.2V that no SELs were observed through all the different capacitor configurations, though having a series resistance to isolate the 10nF or 100nF decoupling capacitor from the rest of the bus capacitance is helpful from a redundant protection perspective.

    For supply voltages greater than 5.2V, is the takeaway then that despite the protection of the series isolation resistance, when the bulk capacitance is sufficiently large and close to the device there is still some latent possibility of a particle strike causing an EIPD that results in latchup? In this case it becomes a matter of sizing the series resistance to maximize protection and device function while taking steps to minimize bulk capacitance on the supply voltage?

    Best,

    Frank

  • 0 in reply to Frank Wangberg
    TI__Guru* 76401 points

    Hi Frank, 

    Frank Wangberg said:
    In this case it becomes a matter of sizing the series resistance to maximize protection and device function while taking steps to minimize bulk capacitance on the supply voltage?

    Yes. supply rail greater than 5.2Vdc remains some SEL/EIPD risk even with series-isolation, especially if bulk capacitance is large and placed next to the Vcc pin. 

    Based on the SEE report finding, we can do a conservative scaling for the size of local cap at the supply pin with the following two constraints.

    1. We can calculate the energy of the local capacitor after the series resistor --> based on 0.5*C*V*V, energy stored in a cap, where the energy should be <= 0.5*1uF*5.2^2, which is approx. 13.5uJ.   

    2. We can estimate peak current limit through the supply path/clamp, where Ipk_limit is < Vsupply/(Risolation + R_path_of_Vcc) or ≈ 5.2V/5Ω <1.04Apk. To improve a design margin, say that Ipk_limit is taking 60-80% of the DC figure (1.04Apk).

    There is another key Ipk figure from the capacitor next to Vcc, where Ipk = C*(dV/dt) is the key determining factor during the transient current event. So ideally the bypass capacitor next to Vcc should be kept lower up to 100nF range (NP0/C0G type), if Vcc > 5.2Vdc. 

    These are my suggestions if supply rail has to be greater than 5.2Vdc in LMP7704-SP application. 

    If you have other questions, please let us know. 

    Best,

    Raymond