JFE2140: Current noise density

Hi Chris,

Thank you for your kind reply. The picture you provided shows the input referred voltage noise density. My question is about the current noise density. Current noise density is measured with high value gate resistor, say 10-100 GOhm, later the noise of resistor itself is subtracted from the total measured noise. I expected to see the current noise density which is independent of frequency (e.g. as shown in Figure 5 of https://www.ti.com/lit/an/sboa060/sboa060.pdf), maybe with 1/f component. However I got the current noise density, that increases with frequency. I'm trying to understand what I did wrong.

Thank you again

Dimitri. 

Hi Dimitri, 

My apologies. I missed the current noise when I read your question. Art Kay is our noise expert. He has written a book on noise as well as several app notes. I work directly with him and will consult with him today on your question. For the mean time here is his latest app note you might find helpful on the Impact of Current Noise in CMOS and JFET Amplifiers. 

https://www.ti.com/lit/an/sboa570/sboa570.pdf?ts=1757385420542

I will follow up by the end of today on your question. 

Best Regards, 
Chris Featherstone

Hi Chris,

Thank you for providing the link to the application note. My setup fully follows paragraph 7 of the app note "Measuring Low Current Noise Levels". As I measure JFET and not op amp, I follow Fig.5-3  Non-inverting Configuration. Resistor value 10-100GΩ, parasitic capacitance around 0.2pF (PTFE substrate), parasitic resistor capacitance around 0.02pF. Should I take distributed-element model of the resistor into account (instead of lumpred-element one)?

Thank you for your support,

Dimitri

Hi Dimitri, 

I spoke with Art and he recommends the lumped model. He hasn't considered the distributed model approach. The current noise will depend on frequency due to the voltage noise and input capacitance as shown below:

in = Vn/(Xc) ; Xc reduces over frequency and therefore current noise goes up over frequency.

One other thing I should point out that can be a little tricky with the discrete JFET is that the bias current goes very high with a Vds above 5V. The low frequency current noise is dependent upon the bias current. 

In addition the voltage noise will go up with an IDS higher than 10 mA. This has the potential to muddy the waters if the VDS and IDS are operating in these areas. 

I hope this information is helpful. Let me know if there is any clarification needed. 

Best Regards, 
Chris Featherstone

Hi Chris,

Thank you for exhibiting the graph from "Impact of Current Noise in CMOS and JFET Amplifiers" This behavior of current noise takes place in the first stage of feedback amplifier, we are discussing stand alone JFET. In my tests Vds is about 4V and Id=1mA.

Thank you again,

Dimitri 

Hi Dimitri, 

Dimitri said:

we are discussing stand alone JFET

The same concept still applies to the single Jfet as well. The input capacitive reactance decrease over frequency will cause the current noise to increase over frequency in the same way. 

Best Regards, 
Chris Featherstone

"Art of Electronics", 3rd ed. 8.11.3 The EnC noise problem (pages 538-539 "Feedback forces the inverting terminal (with its capacitance Cin to ground) to follow, creating an actual input current In(t)=Cin dVn(t)/dt (where Vn(t) is the op-amp’s input noise voltage); expressed as a noise density, we get In=EnωCin=2πEnCin f."

There is no such mechanism is standalone JFET.

Hi Dimitri, 

We expect that the current noise should rise over frequency due to the capacitive reactance decrease over frequency. I ran this by our JFET designer as well and he confirmed that he would expect it to increase for this reason. 

Best Regards, 

Chris Featherstone

Hi Chris,

Thank you for your note, I had a look on the old publications of van der Ziel.  It is always good to remember that not only Cgs and Cgd determine current noise density, but circuit components and parasitics as well. The published current noise density is valid for the ac shorted drain, source and ground, for other circuits (e.g. follower, amplifier, etc) it may differ.

Thank you for productive discussion,

Dimitri

Hi Chris,

Is this correct measurement setup?

1) Set Vds with SMU1

2) Set Id with SMU2

3) With the help of AC Source measure frequency response and calculate Z, seen by gate (R||(Cparasitic+Cgs+Cgd)) and the stage gain

4) Measure noise with the FFT box

5) Take the measured noise, divide by the impedance vs. frequency and gain

6) Post process resulted current noise to remove the impact of resistor R noise current 

Thank you!

Hi Dimitri, 

That is the setup, however it is in open loop and my coworker that made that measurement said he preferred my closed loop solution from my app note because the gain is predictable and doesn't rely on the gm of the JFET. The circuit that was used to collect the PDS data is shown in the JFE150 PDS:

Below is my app note on the closed loop circuit where you can set a predictable gain. This app note is for the single JFET setup you showed above. I wrote it for the JFE150 but the circuit analysis is the same when using a single JFE out of the JFE2140. 

JFE150 Ultra-Low-Noise Pre-Amp

For the JFE2140 I wrote an app note for a somewhat similar circuit. 

JFE2140 Ultra-Low-Noise Preamplifier

Some important notes is that you need very heavy filtering on the supply line or an extremely clean power supply. There is zero PSRR on the JFET and any supply noise will mess up the measurements. My noise measurements on the EVM were done after a 20 minute wait after power up in order to let the long RC time constant settle of the heavy supply filtering. We even did this with a battery. 

In addition averaging with an oscilloscope matters and Art Kay demonstrates this in the below power point. He also shows the method of using a paint can for shielding the circuit from the environment. Things such as lighting in the room can affect the measurements by coupling noise into the circuit. All that to say, special care should taken into account when making noise measurements. 

Op-Amp Noise and Measurment_Oct_2013 (1).pdf

Best Regards, 
Chris Featherstone

Hi Chris, 

Thank you for your important links

May I ask whether my setup and procedure are good for measuring current noise density?

Hi Dimitri,

Yes that setup will work. What you can do is

1. ground the gate with no resistor
2. Measure the op amps output which will be the voltage noise gained up
3. Divide the measurement by the gain and that is the voltage noise
4. Put the resistor in that you have and measure the op amps output again. That is the current noise (converted to a voltage) and voltage noise gained up
5. Divide by the gain to refer the measurement back to the input
6. Subtract out the theoretical thermal noise of the resistor.
7. Subtract out the voltage noise 
8. Convert the leftover back to current and that is the current noise

Best Regards, 

Chris Featherstone