• State TI Thinks Resolved
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 47 subscribers
  • Views 39 views
  • Users 0 members are here
Support feedback
Options
Options
Related

TPA3129D2: Confused about analogue power supply & shutdown logic circuitry.

Michael Feighan
Prodigy 10 points
Part Number: TPA3129D2

Tool/software:

Hi I'm quite new to all this.

I'll be referencing the TI Datasheet throughout.

My confusion stems from the wording on the pin description. For the SDZ pin and other logic pins it reads, "TTL logic levels with compliance to AVCC." To me this means I should pull up the pin with avcc. So my first question is how do I connect those 2? Is it simply from the avcc pin?

My second question is about part 7.3.10 Short-Circuit Protection and Automatic Recovery Feature which says I can achieve automatic recovery by directly connecting SDZ and FAULTZ. My question is where should that connection be? And can I similarly pull up FAULTZ with avcc?

Lastly I got confused over Figure 36. in part 8.2 Typical application. Here the SDZ pin is being pulled up by GVDD. This confused me, despite also the SDZ, FAULTZ and MUTE pins being pulled up by GVDD in Figure 28. Section 7.3.10. The reason this confused me is because in the pin description for GVDD is states that it is "Not to be used as a supply or connected to any component other than a 1 μF X7R ceramic decoupling capacitor and the PLIMIT and GAIN/SLV resistor dividers." So I'm wondering why it is used that way in the datasheet schematics. And if I can't use GVDD, how do I connect AVCC to my logic pins to pull them up high?

bonus question! Can i just tie MUTE to ground if I never intend to add a mute function?

Thanks for reading all that.

  • 0
    TI__Mastermind 18340 points

    Hi Michael,

    I will address your questions below:

    1. TTL logic refers to transistor-transistor logic levels, where typically a 5V supply is used. 2V to 5V would be considered a high, and 0 to 0.8V would be considered low.

    In this case the SDZ can be pulled up as high as the PVCC voltage. Since the SDZ needs to be pulled high to enable the outputs, tying it to PVCC or AVCC is a simple way to pull the SDZ pin high. You can tie to AVCC using a resistor such as 499kOhm. 

    2. Here's a snippet from the TPA3129D2EVM. There's a jumper to tie the SD and FAULTZ pins together, both are pulled up to PVCC but you can pull up to AVCC as well. 

    3. I think this is a mistake in the schematic, GVDD is an internally generated voltage supply so I wouldn't recommend loading it as mentioned in the pin description. I would pull up SDZ, FAULT, and MUTE pins to PVCC or AVCC. 

    4. You can certainly tie the MUTE pin low to ground if you don't want to use it's functionality. 

    Regards,

    Sebastian