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TAS2110: Capacitor Selections for Application Circuit

Tom Zagotta
Prodigy 20 points

Part Number: TAS2110

There are some documentation errors that are making it hard for us to design our circuit using TAS2110.

  1. In the data sheet, the schematic in Figure 50 is out of sync with the list of recommended components in Table 272. This can be seen in SLASET8 December 2019.
  2. In the TAS2110EVM User's Guide, the schematic in Figure 10 is also out of sync with the bill of materials in Section 9. This can be seen in SLAU809 June 2019.

With these two errors, and the very terse descriptions of the external capacitor requirements in the datasheets, it is hard to design a circuit with any confidence it will work properly.

Can you please provide a corrected datasheet and/or a set of proper design files for the TAS2110EVM.

Thank you!

  • 0
    TI__Guru** 114635 points

    Hi Tom,

    Thanks for sharing this feedback on the documentation.

    Section 9.2 is still the main source of information for design recommendations. I'm adding below notes on the content for Table 272:

    • L1: The comments provided are correct
    • R2, R3: These should be named "L2, L3" instead.
    • C1, C2, C3, C3: Boost input capacitor is a single component. Should be only "C1".
    • C6, C7, C9, C15, C16: Boost output capacitor is also a single component. Should be only "C2".
    • C13, C14: These should be named "C3, C4" instead.
    • C5, C8: VDD decoupling capacitor is a single component. Should be only "C5".
    • C11, C12: DREG decoupling capacitor is a single component. Should be only "C6"
    • C10: GREG capacitor should be named "C7" instead.

    For PCB layout guidelines you can refer to TAS2x63QFN Schematic and Layout Guidelines (Rev. A). This is a different device, but pinout is very similar, most of the same guidelines can be applied to TAS2110 as well.

    Best regards,
    -Ivan Salazar
    Applications Engineer