OPA202: IOS Input offset current characteristics

Ninomiya-san,

For Q1, I don't know, I agree it does not align with the spec.  The spec. is tested at final test, so I believe that the typical curve is likely incorrect.  I will check with the team. 

For Q2, I agree, this device does not appear to have input bias current cancellation, because there is an average value for positive and negative bias that is equal.  I checked some test data and can see that on average the bias current is 150 pA for both inputs.  Since the offset current is specified as smaller than the average bias current, then there could be a benefit from adding matching source resistance.  However, this would only help for large source resistance (i.e. 1 MOhm), but then the additional resistor would also increase noise, which would then impact the overall resolution negatively.  So, the OPA205 is still overall a much more accurate solution.

Do you have a specific circuit in mind, or you were just evaluating the devices with the customer?

Regards,
Mike

Hi Mike-san,

The customer wanted to refer to Figure 11 for variation of offset current due to temperature.
If they want to talk about it, it is very helpful to see test data for multiple units of the OPA202.

The intended circuit is a circuit that divides a DC voltage of up to 100 V by 9M ohm : 1M ohm and buffers it with Unity gain.
It has a resolution of 1 μ V as referred to as an op amp input.
The system compensates for the initial offset, but is concerned about temperature drift (0°C to 40°C).
OPA145, OPA205A, OPA202, and so on, they combine the effects of offset voltages and bias currents to determine which ones are likely to have the lowest drift.
Zero-drift amplifiers are excluded because the stability of the bias current is poor, they think.

Best Regards,

Koshi Ninomiya

Ninomiya-san,

I understand the challenge, I agree with everything you have said.  Generally zero-drift amplifiers are not recommended for very high input impedances, but achieving sub 1 uV offset error across 40 degrees is quite difficult otherwise.  

I found the following characterization data, showing input bias current with +/- 18 V supplies, with the inputs at 0 V.  The Y axis is current in nA, X axis is temperature in Celsius.

The IB is very low in this data, then it shows it going negative at hot.  I suspect the variation at hot is due to the ESD cell leakage.  But overall, bias current is quite low for all devices.

I imagine this will generate a long list of questions, I'll try to answer as much as possible but this is all of the data I am able to provide at the moment.

Regards,
Mike

Hi Mike-san,

Thank you for submitting your data.

Feedback from the customer is as follows,
As we have discussed from the beginning, what we expect from the OPA202 is offset current rather than bias current, in other words, the stability of the difference between IBN and IBP in the same device, based on the premise of matching the source resistance.
With the device-identified IBN and IBP numerical data, it is easy to calculate the offset current, but unfortunately I cannot calculate it from the image data provided.
If it is all the data that the previous data can provide, it can not be helped.
The temperature range of 0°C to 40°C is the expected operating temperature. In fact, the offset variation between 20°C and 25°C should be within 1 to 2 μ V.
For the time being, I would like to evaluate it with an actual board, but I think it is good to correct the data for Figure 11 in the datasheet of the OPA202.

Best Regards,

Koshi Ninomiya