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INA700: Clarification on additional hold time on I2C interface for certain I2C addresses

Richard Day1
Intellectual 265 points

Part Number: INA700

Hi all,

The INA700 datasheet states:

"When connecting the A0 pin to SDA to set the device address, an additional hold time of 100ns is needed on the MSB of the I2C address to provide the correct device addressing"

In our testing, this hold time needs to be added between the first falling edge of SCL, and SDA rising for the MSB of the address.

In the diagram below, we have added hold time at point 'a' whereas the datasheet appears to mean it should be added at point 'b'.

i2c_timing (002).png

Adding holdtime at point 'b' is not possible with our I2C controller (and likely most hardware based I2C controllers) because once the controller and data is configured, it will run at the specific clock rate with no opportunity to add hold time to bits.

Is what we are doing valid? Is it correct and guaranteed to work reliably?

Thanks,

Richard.

  • 0
    TI__Mastermind 30795 points

    Hello Richard, 

    This thread appears to be a duplicate thread with this one:  https://e2e.ti.com/support/amplifiers-group/amplifiers-internal/f/amplifiers-internal-forum/1610542/ina700-i2c-timing-clarification/6215958 

    The additional hold time is from the minimum time in the datasheet for t_HDDAT (location b from your diagram), so it's possible that your MCU already has the appropriate amount of hold time. If your hold time is at least the minimum hold time plus 100ns, then no additional adjustment is needed.

    Regards,

    Mitch

  • 0 in reply to Mitch M
    TI__Mastermind 30795 points

    Hello Richard, 

    I noticed that you marked this thread as not resolved, did you still have more questions?

    Regards,

    Mitch

  • 0 in reply to Mitch M
    Intellectual 265 points

    Thanks Mitch, I was in the process of composing a reply but I ran out of time!

    Unfortunately, I cannot access the link you posted, I just get 'Access Denied', so I cannot determine whether it answers my question.

    Further, we have collected some more data which shows the issue and illustrates where adding the hold time works and does not work.

    Each image shows one capture of the I2C address byte, with extra hold time added at point a or b (before or after the MSB, as per previous discussion), with different addresses. The top plot in each image shows the full trace, and the rest are just zoomed in on one edge.

    The images represent, in order:

    - A0 = SDA, extra hold time at a, success (ACK)
    - A0 = SDA, extra hold time at b, fail (NACK)
    - A0 = GND, extra hold time at a, success (ACK)
    - A0 = GND, extra hold time at b, success (ACK)


    This implies that the extra hold time is required at a rather than b, which contradicts the previous interpretation of the datasheet.

    As far as we can tell, all traces except the first meet the timing requirements specified in the datasheet, but we could share the data is you would like to look closer.

    The overshoot and ringing is just due to poor probing, and shouldn't affect the results. The calculated hold time is based on the specified 0.4V and 1.2V low/high input thresholds. The used hold times are small (but within spec), because otherwise the issue does not occur.

    I can provide these images as a PDF if required but I was unable to attach it to the post.

    Thanks,

    Richard.

  • +1 in reply to Richard Day1
    TI__Mastermind 30795 points

    *Edited 2/25/2026*

    Hello Richard,

    Sorry, I didn't realize that the other thread was internal. The reason that you are seeing communication only work when you add time to location "a", is that your timing for location "a" seems to be too short. The datasheet doesn't seem to have a specific time defined for that transition, but looking at the other timing specs, it looks like the time would be calculated as as t_LOW - t_SUDAT. T_LOW has a minimum value of 1300ns, and t_SUDAT has a minimum time of 100ns. If using the minimum for both values, that would put the time at position "a" at 1200ns.  Since these values don't have maximums defined we don't have any way to tell what the minimum time at position "a" would be. So, I recommend adding some padding there to get a reliable communication.  

    The 100 ns addition at location "b" is still needed with an address pin at SDA to guarantee successful communication. It is still possible that it may communicate without the additional time, but needs the time to guarantee communication. Note, this is in addition to the 10ns minimum time, so 110ns total minimum time with using SDA as an address pin. 

    Regards,

    Mitch

  • 0 in reply to Mitch M
    Intellectual 265 points

    Thanks for the response Mitch, it now makes sense, especially with the 1300ns timing requirement.

    We've come to the conclusion it is not possible to use the device in this configuration (using SDA as the address pin, the I2C controller does not support additional hold times being added) and we will have to re-track the board to use a different address pin to avoid this additional requirement.

    Thanks,

    Richard.

  • 0 in reply to Richard Day1
    TI__Mastermind 30795 points

    Hey Richard,

    Ok, I'm glad it makes sense now. Let me know if you have any further questions. 

    Regards,

    Mitch