Part Number: TLV3901
hi,
I am designing HW with TLV3901.
We are designing the circuit under the following conditions.
1. The +1.0 Reference Voltage is entered in the VN pin.
2. A signal of 0 to +1.5V is input to the VP pin while random swinging.
3. The CML output is input to the Zynq(FPGA) chip through AC coupling.
Please refer to the attached file for the design circuit.
Question
1. Are the VCCI, VCCO, and VEE voltage levels correct?
2. I want to use the Latch function, how should I design the circuit for those pins?
3. If you have any recommended circuits or values, please reply.
Thank you.
