Part Number: TLV9152-Q1
Other Parts Discussed in Thread: TLV9152
Hi teams,
I would like to ask about an unexpected behavior observed with TLV9152‑Q1 under an abnormal input condition.
OPA inputs IN+ and IN− (Pin5 & Pin6) are intentionally shorted together (fault injection / stress test).
This condition is understood to be outside normal operating conditions.
Observed Behavior
Two TLV9152‑Q1 samples show different behavior under the same test condition:
Sample A
With IN+ / IN− shorted:
OPA output / MCU I/O remains logic LOW
Behavior is as expected due to MCU pull‑down.
Sample B
With IN+ / IN− shorted:
OPA output (PIN7) / MCU I/O is pulled up to ~3.3 V (logic HIGH)
As a result, the MCU detects I/O as HIGH.
Verification Performed
To rule out MCU-related causes:
The series resistor R26 was removed, disconnecting the OPA from MCU.
Result:
Both samples show identical MCU behavior.
MCU I/O pin briefly goes HIGH (~20 ms) during MCU power‑up, then is pulled LOW by the internal 100 k pull‑down.
This confirms:
MCU reset / firmware / internal pull configuration is not the source of the difference.
The difference only appears when TLV9152‑Q1 output is connected.
Questions
Why do these two samples exhibit different behaviors?
Is this difference caused by sample‑to‑sample variation in the op‑amp output current when the inputs are shorted, resulting in one MCU IO being pulled above VIH (logic HIGH) while the other remains below VIH (logic LOW)?
