TLV3601: Recommendations for TLV3601 Design (II)

Hello Charles,

Is the clock and 2V reference generated on the circuit board or does ether go to a connector?

The TLV3601 that do not perform as expected may have been damaged.  

Hi Ron,

1. The clock signal comes from the onboard oscillator, while the 2V reference voltage comes from an external source (e.g., power supply).
What impact do you think this will have on the TLV3601?
If it must be powered externally, how can we optimize it (e.g., current limiting)?

2. We also suspect that the TLV3601 is currently damaged, so we want to understand the possible causes and improve it. Based on the current failure phenomenon, we suspect IN-PIN damage, causing the TLV3601's output signal to always be high.
Do you think there are other possible causes?

3. Does the operating voltage conform to the recommended values ​​in the TLV3601 datasheet?
(VCC = 3.7V; VEE = 1.0V; IN+ = 1.5V~2.5V; IN- = 2.0V)

4. If it's an output overload, what is the minimum current (mA) required to damage the component?

5. If there is voltage overshoot, What voltage range is considered safe?

6. Specifically, what are the electrical specifications for the IN- PIN?

7. Since the IN- PIN is expected to draw almost no current, is current limiting necessary? (e.g., 1mA)

If there's anything else I haven't thought of, please let me know. Thank you.

Charles,

The 2V source is independent of power pin power up. At least 1k resistance is needed for 2V preceding power up of VCC. 

Adding redirecting diodes will be even more helpful. R1 helps protect D1, D2 and all of it helps protect IN- pin. Both EOS for 2V being outside comparator supply and possible ESD can cause issues. Below gives some ESD protection and good EOS protection for expected input range. 

Charles7 Liu said:

(VCC = 3.7V; VEE = 1.0V; IN+ = 1.5V~2.5V; IN- = 2.0V)

This is 2.7V supply with input voltage within power rails. This is fine.

Charles7 Liu said:

If it's an output overload, what is the minimum current (mA) required to damage the component?

It is possible that the output was the cause. I do not have a current in mind. AMR table 6.1 note 3 may be helpful 

Charles7 Liu said:

Specifically, what are the electrical specifications for the IN- PIN?

7. Since the IN- PIN is expected to draw almost no current, is current limiting necessary? (e.g., 1mA)

The AMR table, section 6.1 on page 5 of the data sheet show this. be sure to read note 2. 

Hi Ron,

I am currently working on a design using the **TLV3601** and have some technical questions regarding the input pin behavior, absolute maximum ratings, and power sequencing. I would greatly appreciate your insights on the following items:

**1. ESD Diode Conduction (Input Above VCC)**
Is my understanding correct that if the voltage on the IN+ or IN- pin exceeds VCC +0.3V, the internal ESD protection diode will turn on, causing current to flow from the input pin into the VCC rail?

**2. ESD Diode Conduction (Input Below VEE)**
Similarly, if the voltage on the IN+ or IN- pin falls below VEE -0.3V, will the internal ESD diode conduct, causing current to flow from the VEE rail out to the IN+/IN- pin?

**3. Risk of Device Damage with External DPS (No Current Sinking Capability)**
In our test setup, the device is powered by an external Device Power Supply (DPS). This DPS lacks current sinking capability, meaning current cannot flow back into the DPS channel. If the scenarios described in Q1 or Q2 occur, the reverse current will have nowhere to go. Will this reverse current cause an overvoltage condition on the VCC or VEE rails?
In this case, does the TLV3601 face a high risk of permanent damage due to voltage rail-up?

**4. Power-Up/Down Sequencing Optimization**
Due to hardware design freeze, we cannot modify the physical PCB layout at this stage. Instead, I have optimized the power-up and power-down sequences combined with the DPS current limit to ensure the inputs stay within the recommended operating voltages as much as possible.
As shown in the attached waveform/diagram, during both power-up and power-down transitions, the voltages on IN+ and IN- are successfully maintained between VCC +0.3V and VEE -0.3V. Based on your experience, is this proposed sequencing viable and safe for long-term reliability?

**5. Alternative Sequencing and Current Backflow Concerns**
If I modify the power-up sequence to turn on VCC, VEE, and Vref first, and leave the 3V3 supply line (connected via a 1.2k ohm resistor to IN+) to turn on last:

* When IN+ is still at 0V (before 3V3 is turned on), will there be a current path flowing from VEE through the internal diode to IN+, and then through the 1.2k ohm resistor toward the 3V3 DPS channel?
* If the 3V3 DPS blocks this reverse current due to its anti-backflow characteristic (cannot sink current), what will be the resulting behavior or impact on the TLV3601 and the node voltage?

Thank you for your time and support. I look forward to your professional recommendations.

Charles,

Charles7 Liu said:

**1. ESD Diode Conduction (Input Above VCC)**
Is my understanding correct that if the voltage on the IN+ or IN- pin exceeds VCC +0.3V, the internal ESD protection diode will turn on, causing current to flow from the input pin into the VCC rail?

Yes most or all current goes to VCC rail. It is possible that some goes to VEE

Charles7 Liu said:

**2. ESD Diode Conduction (Input Below VEE)**
Similarly, if the voltage on the IN+ or IN- pin falls below VEE -0.3V, will the internal ESD diode conduct, causing current to flow from the VEE rail out to the IN+/IN- pin?

Yes most or all current comes from VEE rail. It is possible that some comes from VCC rail

Charles7 Liu said:

**3. Risk of Device Damage with External DPS (No Current Sinking Capability)**
In our test setup, the device is powered by an external Device Power Supply (DPS). This DPS lacks current sinking capability, meaning current cannot flow back into the DPS channel. If the scenarios described in Q1 or Q2 occur, the reverse current will have nowhere to go. Will this reverse current cause an overvoltage condition on the VCC or VEE rails?
In this case, does the TLV3601 face a high risk of permanent damage due to voltage rail-up?

I assume that "device" means TLV3601. The VEE bus might require the DPS to sink current. The total VEE current might be sourcing or sinking. The resulting VCC or VEE will be less than input voltage that causes it. 

Charles7 Liu said:

**4. Power-Up/Down Sequencing Optimization**
Due to hardware design freeze, we cannot modify the physical PCB layout at this stage. Instead, I have optimized the power-up and power-down sequences

This looks okay. 

Charles7 Liu said:

* When IN+ is still at 0V (before 3V3 is turned on), will there be a current path flowing from VEE through the internal diode to IN+, and then through the 1.2k ohm resistor toward the 3V3 DPS channel?

The current can only be used by 25MHz OSC. 

Charles7 Liu said:

* If the 3V3 DPS blocks this reverse current due to its anti-backflow characteristic (cannot sink current), what will be the resulting behavior or impact on the TLV3601 and the node voltage?

Assuming OSC wont be running from IN+ voltage through 1.2k ohms, current will be limited by 9.1k ohms and whatever current 25MHz OSC uses.

Dear Ron,

Thank you very much for your valuable recommendations and the protection circuit diagram.

1. Regarding your proposed solution with the redirecting diodes (D1, D2) and resistors, I would like to consult you on a constraint in our specific design environment. As mentioned previously, both our VCC and VEE rails are powered by an external DPS, which lacks current sinking capability. If we implement the D1 diode, the reverse current redirected from the input source still cannot flow into the DPS channel. We are concerned this might instead cause a voltage rail-up on the VCC line, potentially leading to other over-voltage risks.

Furthermore, our hardware stage makes it extremely difficult to add multiple components. Given that our Vref(DPS) will be set to 2.9V, would it be acceptable if we ONLY add a single 3k ohm series resistor connected directly between the Vref source and the TLV3601 IN- pin? As shown in the attached schematic.

Under our specific biasing conditions (Vref = 2.9V), our calculation shows that even during the worst-case power-up mismatch (e.g., when Vref = 2.9V is fully up and VCC & VEE = 0V), a 3k ohm resistor will limit the forward current through the internal ESD diode to less than 1mA.
I = (2.9V - 0.3V) / 3k ohm ≈ 0.87mA
With such a minimal leakage current (less than 1mA), it should be safely tolerated and absorbed by the TLV3601’s internal ESD structure without any risk of device damage. At the same time, this tiny current will not pump up our VCC or VEE DPS rails.

Specifically, we would appreciate your feedback on:
　* Whether this 3k ohm single resistor is fully sufficient to protect the TLV3601 during power transitions.
　* Whether adding a 3k ohm resistor at the IN- pin will introduce any negative impacts on the comparator's performance (such as propagation delay, response time, or susceptibility to noise, considering the interaction with the pin's internal input capacitance).

2. For your reference, the attached image illustrates our complete connection and operating conditions:
　* IN+ Pin: Driven by a 25MHz OSC via a 1000pF AC-coupling capacitor, with a 1.2k ohm / 9.1k ohm resistor divider for DC biasing.
　* IN- Pin: Connected to (DPS) Vref (2.9V) via the newly proposed 3k ohm resistor (highlighted in red).
　* Power Supply: VCC = 4.4V (DPS) ;
　* Power Supply: VEE = 1.3V (DPS) with an external 15mA current sink.

Based on this current design and our power-up sequencing conditions, could you please help review if there are any hidden engineering risks that we might have overlooked?

Thank you for your time and continued support. I look forward to your professional insights.

Charles,

the 3k can be changed to 1k or 1.2k because that is the impedance on IN+.  If you want to limit AC effect of resistance, you can add IN- to VEE cap. 1000pF makes it same as IN+ side. 

This should be a good combination for performance and device safety.

Dear Ron,

Thank you for your detailed suggestion regarding the 1.2k ohm resistor for impedance matching and the 1000pF capacitor to VEE for AC symmetry.

After reviewing our testing environment, I have a concern regarding the 1000pF capacitor. If power-up and power-down sequencing cannot be strictly and perfectly synchronized, and our VEE rail has a constant 15mA current sink attached, we are worried that adding this 1000pF capacitor might introduce more risks than benefits during power transitions:

1. During Power-Up/Down Transients: If Vref (2.9V) and VEE (1.3V) do not rise or fall at the exact same time, this 1000pF capacitor will experience rapid charging or discharging cycles. The transient current passing through the 1.2k ohm resistor might cause voltage dips or ripples on the Vref line, depending on the DPS dynamic response.
2. Under 15mA Current Sink: If VEE is pulled down aggressively by the 15mA current sink while Vref is still transitioning, the capacitor's energy displacement might affect the stability of the node voltages.

In practical testing, ensuring system survival and avoiding DPS anti-backflow errors is our highest priority. If we decide to optimize for safety and eliminate these transient variables, would it be acceptable to OMIT the 1000pF capacitor and ONLY use the single 1.2k ohm series resistor?

How much impact would omitting this capacitor realistically have on the TLV3601's jitter or propagation delay when operating with a 25MHz input signal? Can this impact be considered negligible?

I would highly appreciate your professional engineering perspective on this trade-off.

Charles,

1000pF energy is tiny. DPS are not instantaneous. There is series resistance; I see no consern. Terminate IN- cap to ground if this is too worrisome. 

Even If VEE was pulled up to 3V on purpose, would anything bad happen to DPS? I would expect it to tolerate such a thing.  

Hi Ron,

Hope you are doing well.

We are finalizing our test setup for the TLV3601 (25MHz clock application) using a Dynamic Power Supply (DPS) that operates purely as a current source (no sinking capability). Based on our recent bench evaluations and the attached schematic, we observed some critical behaviors and would like to confirm the following hardware details with you:

1. VEE Rail Dynamic Current Verification:
Based on our current analysis of the push-pull output stage and the 7 mA max quiescent current (ICC) specified in the datasheet, we calculated the return current flowing into the VEE pin under two steady states:
* Output High State: The return current into VEE is purely the internal ICC, which is ~7 mA (Max).
* Output Low State: With Vout_low measured at 0.4 V across the 200 Ω load, a 2 mA load current is sourced from VEE to GND. This reduces the net return current into the VEE pin to ~5 mA (7 mA - 2 mA).

Could you please confirm if our understanding of these VEE current dynamics (~7 mA at High / ~5 mA at Low) is accurate?

2. Necessity of VEE Bleeder Resistor (Rbleed):
Since there is return current flowing into the VEE pin during operation and our DPS lacks current sinking capability, we plan to connect a 100 Ω bleeder resistor in parallel from the VEE rail (1.3 V) to GND. This will provide a passive constant leakage path of 13 mA (1.3 V / 100 Ω) to ensure the net current seen by the DPS remains positive across all operating states. Please let us know if you have any feedback on this implementation.

3. IN- Node Modification:
To stabilize the node and prevent back-charging into the VEE plane, we will terminate the 1000 pF filter capacitor at the IN- pin directly to GND (instead of VEE) while keeping the 1.2 kΩ series resistor. Please let us know if this implementation is acceptable and if you see any adverse impact on signal integrity or common-mode noise rejection.

Thank you for your valuable insights and continuous support.

Charles,

Now that I see the whole circuit, I have to question, why is the VEE is 1.3V? It is not needed to make 0.4V, 1.4V

With a single 5V supply, VOUT is 0.4V and 1.4V.  This could also work with a 4.4V supply. 

The resistors can also be changed to provide a specific output impedance.