OPA2828: Current Noise Spectrum

James,

Here are a few comments that may be helpful:

1. For the JFET and CMOS devices the current noise is extremely low.  For older devices this noise was generally taken from IC design simulation.  For some new devices it is measured.  Typically, it would be measured for devices that are designed to have extremely low DC bias current.  These kinds of devices are designed for very high source impedance applications such as pH sensors.  Impact of Current Noise in CMOS and JFET Amplifiers covers the topic or current noise and how it is measured for these kinds of devices.  See OPA928 for an example of a device where current noise is measured.
2. For your application you should test to see if the typical current noise is important or negligible.  Multiply your current noise by your source impedance to see what noise voltage this converts to.  Compare this to the thermal noise of your source impedance and also to the thermal noise from the op amp.  For most applications, the thermal noise from the source impedance will be much greater than the current_noise x source_impedance.
   1. Thermal noise density can be calculated using the equation en = sqrt(4*k*T*R).  Where K = 1.38E-23 (Boltzmann's constant), T is temperature in Kalvin.  
3. For op amp noise vs JFET noise this paper is a good reference:  JFE150 Ultra-Low-Noise Pre-Amp .  The JFET has the flexibility of changing the biasing which will change the input noise.  Some op amps are designed for very high bandwidth and low noise.  These amplifiers have high quiescent current.  Bipolar op amps have an advantage over JFET and CMOS from a noise vs IQ perspective.  Conversely, JFET and CMOS have a current noise advantage over bipolar amplifiers.  JFET amplifiers have an advantage over CMOS amplifiers for 1/f noise.  There are many strengths and limitations of the different technologies.  One of the big advantages of the JFE (discrete JFET devices) is that you can control the biasing yourself whereas you cannot control internal biasing of a monolithic op amp.

I hope some of this information helps.

Best regards, Art

James,

1. The improvement of op amp noise has been a gradual process.  Keep in mind that noise is not necessary the only or primary concern in the op amp design.  Often there are many different factors that require tradeoffs to be made on noise performance.  The nice thing about the JFE devices is that you can make your own tradeoff decisions. You really need to seporate out current noise from voltage noise when thinking about the historical improvement in noise performance of op amps.  
   1. For bipolar devices current noise will be much higher than CMOS or JFET.  Generally, I don't even consider the impact of current noise on CMOS and JFET devices. The improvement CMOS and JFET current noise has not been a major research area because the values are inherently very low.  For some devices, such as OPA928, the current noise was considered because the device will be used with very high impedance sensors. 
   2. For bipolar devices improvements in current noise have been made recently using super-beta technology.  The OPA205 (2023) uses super-beta transistors to reduce bias current and current noise (en = 7.2nV/rtHz, in = 110fA/rtHz).  Some bipolar devices will use bias current cancelation.  This will decrease bias current but actually increase current noise.  The way bias current is decreased is to inject current into the base to cancel the bias current.  This reduces the DC bias current but the current noise of the base current and injected current are uncorrelated and add rather than subtract.  In general, bias current noise on bipolar is much higher than CMOS and JFET because the bipolar device requires base current to operate.  Improvements such as super beta can help but bipolar current noise will always be much higher than CMOS.
   3. Around 1992 OPA277 and OPA227 were very low noise bipolar devices (en = 3nV/rtHz, in = 400fA/rtHz).  These have very good voltage noise but not great current noise.
   4. Around 2000 OPA627 JFET input was released with very good noise (en = 4nV/rtHz, in = 2.5fA/rtHz).  The current noise is low because it is JFET.  The voltage noise was very low for a JFET type device at the time.
   5. Around 2006 OPA211 was released.  This bipolar device has en = 1.1nV/rHz, and in = 1700fA/rtHz.  This is an excellent voltage noise but as you might expect the current noise is not good.
   6. Around 2018 OPA828 released.  This JFET device has en = 4nV/rHz, and in = 1.2fA/rtHz.
   7. When comparing at the voltage noise of a JFET or CMOS to bipolar, you should look at the 1/f region.  Generally, the 1/f region noise corner will happen at a much lower frequency on a bipolar than JFET.  JFET is better than CMOS.
2. I want to emphasize how current noise is generally negligible.  Below is a calculation where the current noise is 1.2fA/rtHz and the source impedance is 1MΩ.  The current noise converts into a 1.2nV/rtHz voltage noise when it flows through the source impedance.  The source impedance generates a 128nV/rtHz thermal noise.  For this source impedance the current noise will effectively contribute no noise because the voltage noise is significantly larger than the current noise.  You would have to increase the source resistance to 11 Tera Ohms for the current noise to be significant.  The calculation is below but Impact of Current Noise in CMOS and JFET Amplifiers covers this topic in detail.  
3. One last thing to consider with current noise of JFET or CMOS amplifiers.  The input capacitance of an op amp can cause an increase in current noise at higher frequency.  This is due to the voltage noise converting into current noise through the Xc of the input capacitance.  This may cause current noise of CMOS devices to be significant at high frequency in some cases.  This is also covered in the document and is modeled in op amp models. 

Best regards, Art

James,

Below is the current noise spectrum.  You can see the 1/f noise corner is at about 7Hz.  There is a very small flat-band region at about 10Hz.  After 10Hz the current noise begins to increase.  The increase is due to the interaction of the input voltage noise and input capacitance.  This increase is sometimes called f-squared noise or blow-back noise.  Some CMOS/JFET op amp data sheets don't show the f-squared noise in the current noise spectrum, but they all will have this issue in reality.  The reason why it is not always shown in the plots is because it really is a function of the voltage noise and input capacitance so when the op amp is modeled in SPICE the current noise source really does not include the f-squared noise.  However, the SPICE model does show the f-squared noise because it is a biproduct of the input voltage noise and input capacitance.  The point is that the SPICE model will show this increase in current noise and the actual device also shows it.  The plot below was measured using the techniques described in Impact of Current Noise in CMOS and JFET Amplifiers .  Measuring current noise at this level is pretty challenging.  I am confidant in the plot below because it was measured using the approach outlined in the article, but I think for some older devices and competitor devices you might want to double check with your own measurements to confirm.  The measurement method described in the article is a more recent refinement in our measurement approach.  The article also outlines some real-world considerations for achieving this level of current noise in section 8.  Certain factors like PCB cleanliness, humidity, PCB layout, and PCB material may be a factor.  I hope this helps!

Best regards, Art