INA151: PSPICE model

Hi Danilo,

The customer is correct that the stock GWL model has topology-induced convergence problems with PSPICE. We're currently developing separate PSpice-native models for the INA151 family.

As far as the wrapper goes, we agree this is a good architectural direction and would reduce long-term overhead/development time. That said, extra structural elements aren't necessarily incidental in our modeling process, but they can be elements needed to keep the model's simulated performance aligned with the datasheet specs/plots for that variant, as simply changing a gain parameter often doesn't lead to accurate performance across gain variants due to nonidealities seen with real silicon.

For example, C34/35 were included the C version in order to match the small-signal response of what is specified in the datasheet. The extra VCVS blocks were needed to model the correct VCM/VDIFF limitations of the device at variants with a gain < 1.

It would definitely be helpful to see the cleaned-up files. Is the customer having trouble emailing them to you?

Best Regards,

Taylor Allan

Hi Taylor,

Thank you for your response. Please see our customer's feedback.

I don't have any issues with sharing.  I am attaching a PDF of the original GWL model (for the LMV321A, which is where I encountered it) and my updated model.  I have applied this new model to about 10 TI op amps, with great joy. 

GWL op amp model.zip

Some details, there are 4 areas that cause convergence issues:

1) Convergence issues usually first appear as problems in the OL switch control node (SW+ node of the XOL_SENSE) subcircuit, but in reality are with the "MID" voltage generation.

2) The input diff amp gain is completely linear, and so has to be clamped.

3) The output current limit is also clamped at the "CL_CLAMP" node.

4) The output voltage swing is clamped at the "CLAW_CLAMP node.

    Basically this clamp approach doesn't work, because it is way too stiff.  It may be possible to get this to work for linear operation and no fault.  But, it will usually quickly fail, or become very, very slooow, for non-linear or fault conditions.  Remember that PSPICE ABM models switch in one time step, so as the algorithm reduces the time step to attempt convergence, the stiffness increases concomitantly and the simulator chases its own tail into a convergence failure.  This is why Verilog A has a transition time on its ABM models.  Transition times would help, as would quad precision math, making the dynamic range 24 digits instead of 12, but knowledge of the problem usually suffices to avoid topology issues.

      1) Is solved by using ABM to directly create "MID", and only filtering the result.

      2) Is solved by making the diff amp transfer function an ArcTan function.  I guessed at the values, but TI could put in correct values.

      3)&4) (and implicitly) 1), are solved by moving all the clamp functions, overload function to the output amp.

            a) The output current is sensed and used to load the output *before* the output buffer/clamp.

            b) The output current limit and voltage swing are combined into a single output buffer/clamp control voltage.

    Input noise, common mode, offset are unchanged.  However, any control voltages, currents are generated with a distribution.  The resistor model that controls the distribution also allows the addition of a tempco.  I can share these models as well, if desired.

    I hope this gets through, as your server seems (justified in these times) pretty paranoid about attachments.  I can also send examples in the form of the various models I have modified.

Regards,

Danilo