• State Resolved
  • Replies 3 replies
  • Subscribers 48 subscribers
  • Views 73 views
  • Users 0 members are here
Support feedback
Options
Options
Related

OPA818: OPA818 Layout

Shigenori Mizuhara
Prodigy 10 points

Part Number: OPA818

Regarding the input signal layout, the datasheet states the following:

“To reduce this unwanted capacitance, a plane cutout around and underneath the signal I/O pins on
all ground and power planes is recommended.” 

We are designing a multilayer PCB. In this case, should the power and ground planes be removed on all layers underneath the input signal traces?

Or would it be sufficient to create the plane cutout only on the layer directly beneath the input signal traces?

  • 0
    TI__Mastermind 23190 points

    Hi,

    For our four layer boards we recommend cutting out the planes under these sensitive nodes for all the layers not just the layer directly beneath the top layer. I would refer to the EVM we designed specifically for this device as your guide for your PCB. This device is quite sensitive to parasitic capacitance so I do recommend following what we did. For this board we removed the planes under the output pin and anything touching this pin as well as the inverting node. However we did not remove the planes under the feedback pin or anything else touching this pin. I would refer to the layer stackup we highlight in the EVM as this will help make things more clear.

    www.ti.com/.../sbou222a.pdf

    Best Regards,

    Ignacio

  • 0
    Prodigy 10 points

    Hi, Ignacio

    Thank you for your reply.

    I see.

    Best Regards,

    Mizuhara

  • 0 in reply to Shigenori Mizuhara
    TI__Mastermind 23190 points

    Hi Mizuhara,

    No problem, if you need help reviewing the final layout please feel free to reach out and we can look it over.

    Best Regards,

    Ignacio