Other Parts Discussed in Thread: PGA113
Dear All
What are the CMRR specifications for PGA 113?
Thank you in advance.
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Other Parts Discussed in Thread: PGA113
Dear All
What are the CMRR specifications for PGA 113?
Thank you in advance.
Hi Imtiaz,
The PGA113 doesn't have published common-mode rejection ratio (CMRR) specifications because it has a single-ended, non-inverting input and doesn't have differential inputs like a stand-alone operational amplifier, differential amplifier, etc. Nevertheless, the PGA113 internal operational amplifier is required to have and does have very high CMRR. The CMRR is not listed as a dtasheet specification, but instead the error it does produce contributes to the voltage offset error specification. If the CMRR is very high its contribution to the voltage offset will be very small, and vice-versa. Also note the CMRR may be different over the amplifier's input common-mode input voltage range and its contribution to the total offset will change with the amplifier's input level.
Figure 12 in the PGA113 datasheet provides the a plot of Input Offset Voltage vs. Input Voltage. You can see from the plot that the input-referred voltage offset is very low with an input voltage of 0 V to about 3.6 V. Thus, the offset error contributed by the CMRR is small; however as the input voltage is increases beyond about 3.6 V, the voltage offset shows can potentially increase. Any increase in the voltage offset is mostly due to a the amplifier's decreasing CMRR as the upper input voltage limit is approached.
Here is an an CMRR approximation based on Figure 12: If the voltage offset is +20 uV with a Vin of 2.5 V and increases to +75 uV with a Vin of 4.5 V, then the CMRR is about 91 dB. Therefore, it is evident that the CMRR would have to be very high (> 100 dB) withn the region where the input offset error is very low. Most of the offset in that region is due to actual voltage offset and not CMRR contributed error.
Regards, Thomas
PA - Linear Applications Engineering