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Constant current sink/source using LMP7721 and FET

R_Sam
Prodigy 120 points

Other Parts Discussed in Thread: LMP7721

Dear Sir,

Referring to the blog of Bruce Trump I have implement the current source design as mentioned in it. My current range is from 1pA to 1nA.

In this design I used the glass sealed 10G ohm of resistor with 1% tolerance and SD210DE MOFET with LMP7721 op amp. 

The graph shows  current with respect to voltage but it seems to have a noise of 10pA to it. And the Vs is maintained at 10 V. Vref is changed from 0 to 1.5V. This circuit is of current sink. And now I want to implement the circuit of current source, so instead of N-MOSFET I will have to use P-MOSFET. But while selecting P-MOSFET which parameters, I will have to consider. And in the above circuit where I am wrong let me know.

  • 0
    TI__Guru 65176 points

    Hello R_Sam,

    Congratulations! It is actually working very well.

    The problem is the inflection at 15pA is probably the gate leakage of the MOSFET getting in the way (providing a parallel path). A straight resistive leakage would show a softer, flat plateau without the "uptick" at 0V.

    Going down to currents this low means the most important parameters for your MOSFETS will now be the gate/drain leakage specs.

    Where are you connecting "Case" connection? (pin 4).

    Try connecting pin 4 (Case) to the Vref voltage. Theoretically, the drain and the Vref line should be at the same potential under feedback.

    This will act as a driven guard, and any gate leakage will now "leak" into the low impedance Vref line, and not into the sense resistor.

    I am also assuming you have taken all low-current precautions (shielding/guarding).

    When going to the "high-side" current source, be sure to watch the input common mode limits of the LMP7721 - it is not a rail-to-rail input. The legal input range is 2V below V+, but you really want to try to keep the common mode <= 2.5V.

    BTW: In your circuit, you are violating the abs max supply voltage spec. The abs-max is 5.5V, and you are running at 6V. I would be remiss if I did not admonish you to drop the supply to 5V...

    Regards,

  • 0 in reply to Paul Grohe
    Prodigy 120 points

    Dear Sir,

    Thanks for your valued response. Please find the answers below required by you.

    I had connected the pin 4(Case) to the source. I will try to connect it to Vref as you suggested.

    Actually I have not implemented a guard ring on the PCB with LMP7721 but the test circuit is enclosed in the aluminium case to protect it from external noise with all precautions. And also I cleaned the PCB with IPA as suggested in your application note.

    I am running the circuit at a 5V only but as the image of the schematic gets compressed 5V appears as a 6V. 

    Looking forward for your suggestions.

    Thanks & Regards

    Sameer 

  • 0 in reply to R_Sam
    TI__Guru 65176 points

    Hello Sameer,

    Remember that the guard is protection from local circuit leakages. The aluminum box just protects from external and environmental noise & leakage. The guard is what potentially (pun intended) gives you the lowest leakage and best results.

    Have a look at my EDN articles, and chapter 2 of the Keithley Low Level Handbook

     http://www.edn.com/design/analog/4368681/Design-femtoampere-circuits-with-low-leakage-part-one 

     http://www.edn.com/design/analog/4375459/Design-femtoampere-circuits-with-low-leakage---Part-2--Component-selection

     http://www.edn.com/design/analog/4395651/Design-femtoampere-circuits-with-low-leakage---Part-3--Low-current-design-techniques

     http://www.keithley.com/knowledgecenter/knowledgecenter_pdf/LowLevMsHandbk.pdf

    Regards,