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PGA280 SPI timing.

Other Parts Discussed in Thread: PGA280

Hi.

I have been unable to find much information on the SPI timing of the PGA280. 

I have found only two statements in the datasheet.  first is max SPIclk is 10MHz, and data is latched when SPI goes low.

Where can I find information about setup and hold time on the data in, and delay on data out. I there any requirement regarding the CS on delay or similar.

Regards Martin 

  • Hi Martin,

    The lack of detailed timing information in the PGA280 datasheet has been brought to our attention previously. I am currently working with the design team to find this information. I will update this thread when I've found the requested information. 

  • Hi John

    Any progress in defininig timings for SPI?.

    Right now I'm working on project where we are heavelly utilizing this amplifier generating a lot of SPI traffic.

  • We're working on characterizing this now, I will update the thread when we've determined the timing characteristics. 

  • Hello,

    I am working on the SPI bus for the PGA280 to interface with the MPC5644A CPU (CPU is the master). We need timing diagram for the SPI, need to know the followings: PCS to SCK Delay (tCSC); After SCK Delay (tASC); Delay After Transfer (tDT).

    Did this information on SPI timing ever get posted?

    Thanks,

  • Yes, the timing requirements for the PGA280 were finally characterized last week. Please see below:

  • Thanks for the information. But these settings are the minimum settings.

    We need to know if our current setting is okay to operate with this device (over the operated temperature range).

    Here is our current setting for the device (the device is connected to the MPC5644A CPU and the CPU is the mater):

    SCLK   =  0.984MHz ( Clock Period = 1015.9ns; Clock Pulse = 507.9ns)

    Tscs    =  507.9ns

    Tasc   =  507.9ns

    Tdt     =  507.9ns

    Thanks,

  • Sevrum,

    The values listed above are minimums specified over the temperature of the device, going below those values will cause problems in data transmission. However, times longer than those specified above are not a problem as long as they do not violate the minimum setup and hold times given (5ns). The clock timings you have listed should cause no issue over the temperature of the device. 

  • Hi John,

    Can you explain what the Part No 1 vs. 1-3 nomenclature is supposed to mean?  Also, will there be a forthcoming datasheet revision to include this info?

    Thanks,

    Tom

  • Hi Tom,
    The char engineer who took this data did it on three units (Parts 1-3), for specs that were identical for all parts tested I removed 2 of the DUTs from the chart so it was easier to read.

    Currently the product lines are updating a lot of datasheets to the new format mandated by TI. I'll send a message to the systems engineer responsible for this part (Jerry Steele) to see where this falls on his list of datasheet updates.
  • Hi John,

    GE is inquiring about the additional changes as mentioned above. The PGA280 DS still shows Sept 2009. They anticipated that after 8 months we would have implemented these changes and updated the datasheet. Can you comment on this? Is there a problem with the char data? If the data is ok, can you send me the prelim version of the next datasheet to release updated for 2016?

    Thanks,
    Tom
  • Hi John,

    Do you have a plan to release updated datasheet?
    I'd like to confirm the specifications of SPI timing on it.

    Currently it's not updated from Sept 2009 version.
    www.tij.co.jp/.../pga280.pdf

    Best Regards,
    ttd