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IVC102 integration time 1us

Gabriel Koutilellis1
Prodigy 180 points
Other Parts Discussed in Thread: IVC102

Dear community,

I use IVC102 that is powered with +/-15V in order to measure low currents.

Internal capacitors are all connected together and at pin 3. So total capacitance is 100pF.

pin 2 is input,

pin1 is directly connected to analog ground.

With the formula of slew rate in the datasheet and taking 1V/us as maximum, Cint = 100pF then the maximum current to measure is 100uA.

Anyway...I use 3.3V and 10MOhm resistor to produce 0.33uA at pin2. So I tried to integrate for 1 us and I expect the output of IVC102 at pin 10 to be a voltage ramp with a maximum of about -3.3mV (gain = -10,000).

Well...I get a more squarish form with a maximum of approximately 200mV.

If I increase integration time to more than 100 us I get a voltage ramp with the expected voltage value (I mean now g = -1,000,000 so I get about 330mV)

Why does this happen? Any explanation?

Thank you a priori.

Gabriel

  • 0
    TI__Guru* 93105 points

    Hi Gabriel,

    All of your calculations look good relative to the IVC102 operation so that tells me the unexpected output waveform/level has to be happening for some other reason. 

    When I look over the IVC102 specifications I am not finding anything to which I can attribute the unexpected output. It appears as though the IVC102 input may be receiving current from an unexpected source during the 1 us integration period. 

    How do you have the IVC102 circuit constructed? Is a clean PC board circuit with input guarding as shown in data sheet Fig. 4 being used? Is the IVC102 circuit shielded from 50/60 Hz fields? It is easy to corrupt the performance of transimpedance amplifiers if proper precautions aren't observed.

    Regards, Thomas

    PA - Linear Applications Engineering

  • 0 in reply to Thomas Kuehl
    Prodigy 180 points

    Dear Thomas,

    The board is constructed as in fig. 4, yet if 50Hz noise gets into the system, then at 100us integration time there should be more noise (greater gain factor).

    If I use guarded and shielded cable (the guard at analog ground), I could remove the 50 Hz noise completely? (triax connector I guess)

    I noticed somewhere in the datasheet saying on page 6, section about integration on Cint

    The integration period could range from 100us to many
    minutes,

    Could this explain the behavior? And why exists such a limitation?

    Thanks

  • 0 in reply to Gabriel Koutilellis1
    TI__Guru* 93105 points

    Hi Gabriel,

    Do you have the measurement capability to capture and plot the IVC102 output from time 0 to 100 us? We need to see what the output looks like at the onset of integration. If you could do plots from 0 to 1 us, 0 to 10 us and 0 to 100 us that may provide us even more information.

    The transimpedance example on page 6 is centered around a 100 ms integration time. I do not believe that is indicating a limitation on integration time. The transimpedance for a 1 us integration time, and 100 pF capacitor would be 10 k, based on that information.

    Regards, Thomas

    PA - Linear Applications Engineering