INA226

Matt,

I tested our INA226EVM in the lab and found that it behaves as described in the data sheet with regards to the Mask register.  I'll detail my experiments below:

1. reg 0x00 = 0x4127 (defaults, continuous conversions), reg 0x06 = 0x0401 (tying convert ready to the alert pin, alert pin latch enabled, polarity 0) - observed that the alert line was low until we read the registers which pulled the alert pin high.  When we executed that read,, we cleared the convert-ready flag for 1.1mS (default conversion time) and then the alert pin asserted low again and stayed there until another reading was made.

2. Same test as 1 with inverted polarity bit: reg 0x06 = 0x0403.  The same behavior was observed except alert was held high most of the time and pulsed low then back to high when the registers were read.

3. Same test as 1 except with the latch enable bit set to 0: reg 0x06 = 0x0400.  The same behavior was observed.  This is due to the fact that in both latched and transparent cases, the mask/enable register must be read to clear the conversion ready flag and the alert pin.  (Page 22 of the data sheet explains more about what events clear these bits.)

4. Same test as 3 with the polarity bit inverted.  Same results observed except the polarity of the pin was inverted.

5. I set the Mode of reg 0x00 from 7 to 4, making the device convert in single-shot mode instead of continuously.  (reg 0x00 = 0x4123, reg 0x06 = 0x0401).  When I write to the config register, a conversion is started.  When it completes, the convert ready flag bit asserts, as does the alert pin, and stays constant.  when I read register 0x06 after that, I see the convert ready bit is 1, and at the same time, reading that registers clears both the convert bit and subsequently the alert pin, which deasserts.  The process can be repeated by writing the config register again and triggering another single conversion.

6. Same test as 5, with polarity bit inverted.  Same results observed with the Alert pin polarity inverted.

7. Same test as 5 with the Latch Enable bit of register 0x06 set to 0, so reg 0x06 = 0400.  Same results observed.

8. Same test as 7 with the polarity bit inverted.  Same results observed with the alert pin polarity inverted.

I was unable to get the ALERT pin to stick high regardless of setting, so long as I issued the appropriate write and read commands.

I am not sure if this explanation helped with your issue; I expect there is something else, possibly software or hardware related, that is causing the issue.  Would you mind sharing the relevant part of your schematic with me, and possibly your programmatic use case?  If you don't want to share it on this public forum, my direct email address is bridgmon_jason@ti.com.

I look forward to assisting you further!

Jason Bridgmon