LMH6518 Input Buffer

Sebeom Rho

Other Parts Discussed in Thread: LMH6518, TINA-TI

Hello,

I have a plan to design the high speed analog frontend using LMH6518. In the datasheet, JFET LNA has been used in fornt of LMH6518. I would like to use this schematic for our design.

1) Is this LNA circuit has a performance of 500MHz analog bandwidth?

2) If not, Do you have any recommended LNA circuit for 500MHz analog bandwidth?

Thanks, Sebeom

over 11 years ago

0 Hooman Hashemi over 11 years ago

TI__Mastermind 22825 points

Hi Sebeom,

To answer your questions about the JFET LNA (Figure 69 schematic):

The overall circuit (JFET LNA + LMH6518) exhibits > 500MHz for -3dB Bandwidth. However, on the EVM we had used to characterize the circuit, the frequency response flatness shows undulations, as you can see below:

Conditions: Freq Resps HG 20dB Pin=-10dBm J10 Gate_Source cap= 47pF+33pF+10ohm Full_BW R8=210ohm.jpg

Unfortunately, at the time of LMH6518 release, we did not go much further with the JFET LNA optimization to see if we can "flatten" the response some more.

Regards,

Hooman

0 Sebeom Rho over 11 years ago in reply to Hooman Hashemi

Prodigy 150 points

Hi Hooman,

I am glad to hear that the JFET LAN + LMH6518 meet the 500MHz bandwidth. I would like to simulate these circuit using PSPICE. But there are no PSPICE model for the LMH6518 in the TI website. Do you have any idea to simulate these circuit?

Thanks, Sebeom