INA326 - Is it okay to put capacitor between +in and -in?

Hello Charles,

While the INA326 is sensitive to parasitic capacitances on pins 1 and 8, I don't see an issue with a differential capacitor between the inputs because you're connecting it to the non-inverting nodes of the amplifiers.

The values given in the data sheet for single-supply, G=1V/V are R198=400k and R37=200k. Have you tried using these values? This is probably not the issue, but something to rule out just in case.

Finally, have you probed at the input pins of the device (2, 3, and 5) instead of probing before the filter? I am interested in oscilloscope screen captures. Because the INA326 is referred to AGND, please make sure these measurements are also referred to AGND.

Thank you for your response, Pete.  We have not tried the increased values for the resistors.  I have attached the waveforms as requested, as well as a redlined version of the circuit.  This time, it was a different (but identical) circuit that had its output stuck at full scale.  I was not able to probe the INA326 inputs directly because doing so "fixed" the circuit and the output became equal to the input.

Do you think that a glitch of some type on startup could have caused latchup?  The currents into the inverting/non-inverting inputs are limited by the input resistors to values below the absolute maximum.INA326 with redlines.pdfINA326 Waveforms.pdf

Hello Charles,

Is there a dc path for the input bias current?

Yes, there is a path for the DC bias current.

Hello Charles,

Thanks for the additional information. What provides the input signal? Also, what is the input signal's expected amplitude and frequency? Can you replicate the behavior using a function generator?

I haven't heard of any latch up issues with the INA326. The 20kohm resistors should be fine with respect to the input bias current path. Have you experimented with the resistor and capacitor values and obtained correlation between the filter resistor values and the abnormal behavior? Finally, please try using the data sheet recommended values for R1 and R2 and let us know if the behavior still exists.

Pete,

Would you please double-check on the input capacitor latch-up issue: we wonder if the auto-zeroing circuitry may have a problem with the differential capacitance.

An op-amp provides the signal.  The differential amplitude should be limited to 3V, with the negative input limited to -.05V and the positive input limited to 3.05.  So basically a 3V signal that may be referenced a little differently than the instrumentation amplifier ground.  The frequency is DC but there may be some noise.

We tried reducing R1 and R2 by a factor of 2 to exacerbate the problem, but were unable to.  This shows evidence that the resistor values aren't the issue.  Normally, there won't be more than 25uA of current through R2, which seems to be the main concern.  The worst-case would be 30uA, but that's not a large concern since the datasheet says the only effect will be minor nonlinearity in that range, which is okay.

We really appreciate your time and help, Pete.  Have a great day.

Pete,

It looks like this circuit is prone to phase inversion. Would an increase in the input resistors prevent the phase inversion, or will external clamping diodes be required? Also, based on the fact that the output is latching at the positive supply rail, is it possible to determine which input is causing the phase inversion? I was unable to reproduce the phase inversion by manually applying a high voltage (24V) to the non-inverting input.

Pete,

One additional question: The datasheet does not show a supply rise time requirement. Is there one that is simply not specified in the datasheet?

Hello Charles,

Thanks for the additional information and tests.

I have searched our failure analysis database and found no returns due to latch-up for the INA326. Have you tried removing the differential capacitor? If so, does it resolve the issue? I ask because it would take me awhile to build a PCB specifically for the INA326. Due to the device's sensitivity to parasitic capacitance I'd rather not use a protoboard.

Thanks for checking for any correlation between the magnitude of the gain setting resistors and this issue.

Concerning your phase inversion test: you may want to replace the device you're using after applying 24V to the non-inverting input. The absolute maximum voltage that can be applied without compromising the device, given a 3V supply, is 3.5V. It is likely okay if you limited the current, though.

One other idea: try disconnecting the INA326 from the ADC by removing R13, then probe pin 6 of the device with an oscilloscope. Perhaps this is a stability issue, though I assume the 100ohm isolation resistor is sufficient.

Though there is no specification for power supply rise time, it does appear as though another person found that lengthening the rise time to 6ms fixed their issue. It sounds very similar to your issue. Here is the link:

e2e.ti.com/.../345886