Other Parts Discussed in Thread: INA128, ADS8320, ADS1259, ADS1120, ADS1262, ADS1148, ADS1158, ADS1252
I am looking for a solution for the design of a load cell conditioning circuit + ADC for a test machine. Ideally this circuit would have a bandwidth of 200+ Hz and decent resolution (14 bits).
After some research, my understanding is that INA128, powered by a dual supply, might a good fit, due to higher CMMR
In order to keep the system ratiometric, I would like to the ADC to reference the same supply as the load cell bridge. I’m thinking a discrete 16bit SAR ADC, perhaps something similar to an ADS8320, would fit. Since its analog reference voltage can be no grater than 5V, the load cell bridge would then be powered by a +5V single supply.
Now for my problem – what is the preferred means of conditioning signal output of the INA128 to the ADC?
I am having difficultly since the output is not rail-to-rail, but would like to maximize the signal to the ADC.
I could power the INA128 from a +/- 5V supply, which would result in a minimum output range of +/- 3.6V (per shec sheet min). I would then need to offset and amplify this to achieve 0-5V for the ADC. But what if the output range is higher, say +/- 4.1 (per the spec sheet typ)? Would I also need to clamp the voltage?
Thanks in advance!
Mitch.