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Help with PWM OPAMP selection

Ben Popoola
Prodigy 130 points
Other Parts Discussed in Thread: TINA-TI

Hi,

I have an application whereby I use a CPLD to generate four PWM signals. According to the literature, that I've read, I need to buffer each of these signals with an OPAMP and create the equivalent of a low-pass filter circuit. The PWM signals are generated from 16-bit digital logic , which are updated at a frequency of say 120Hz.. The voltage of the PWM signal will be between 0V and 5V.

Being a digital design engineer and given the huge range of OPAMPs available from your website I need help in selecting a general purpose  OPAMP for this application.

Cheers

Ben

  • 0
    TI__Guru* 93105 points

    Hi Ben,

    I haven't ever dealt with a CPLD before, but do understand your need to demodulate the the PWM digital signals coming from its outputs. You should be able to use an op amp integrator for that purpose.

    You stated the digital levels are 0 and 5 V. Can you provide some example of what the PWM timing might look like? It would really be helpful to see the timing associated with the expected PWM signal; the range of low and high times. That has implications for the op amps bandwidth and slew rate.

    Op amps are intended to be operated in their linear input and output ranges. If the input levels are 0 and 5 V and you expect to use a single, 5 V supply, we need to make sure the op amp can support that arrangement. If you plan to use a different supply voltage that would be good to know too.

    Regards, Thomas

    PA - Linear Applications Engineering

  • 0 in reply to Thomas Kuehl
    Prodigy 130 points

    Hi Thomas,

    Thanks for your response.

    Firstly, I should say that although the required analog output levels are 0V-5V, the digital levels will be 0V to 3.3V. Hence, I understand the requirement for a level-shifter, which could be incorporated either as a part of the PWM op-amp circuit, or as a separate first stage op-amp level-shifting circuit. Implementing the first method would push my analog skills to new levels, whereas I could probably cope with implementing the second method.


    With respect to the PWN timing here are my thoughts:

    The rise and fall times of the CPLD are likely to be less than 1ns, probably about 0.45ns to be more precise. If the digital output is required to change at a rate of 120Hz, then the period of the output is 8.33ms. When the PWM signal has a 50% duty cycle it follows that the high and low periods of the output pulse is 4.165ms.

    Likewise, it also follows that if the generated PWM signal has a range of 0 to 2^16 -1 (65535), then the smallest 'ON' time should be 8.33ms/2^16 is approximately 127ns. Does this time information help? Are my demands of the op-amp too ambitious? If need be I could reduce the number of bits used to generate the PWM signals to 12 or 14 bits.

    Regards

    Ben

  • 0 in reply to Ben Popoola
    TI__Guru* 93105 points

    Hi Ben,

    Much of this would be new to me as well. Most signals that I deal with are linear in nature.

    I mentioned an integrator could be used to demodulate the PWM signal. Actually, an integrator has a low-pass response. About a decade ago I used an an active filter that had a low-pass response to demodulate a PWM signal. What is nice about that approach is that it didn't require any reset function like a conventional integrator. So I suspect that a properly specified 2nd-order low-pass filter could be employed at each CPLD output to recover the modulation information from the PWM signals.

    If you think that is an approach you would like to take, TI has a tool for synthesizing active filters. There actually two different tools, but the one I am going to suggest is an older, easier to use tool called FilterPro. It can be downloaded from:

    There is information about the other filter tool, Webench Filter Designer, but you want to navigate until you find FilterPro and its download.

    I expect the low-pass cutoff frequency is going to be fairly low. You mention the digital output is going to be required to change at a 120 Hz rate so that may be a good frequency set the cutoff for starters. I suspect it will have to be lower, but for now that at least gives a starting point.

    The best way to test if the circuit does what is needed is to set it up in a PSpice circuit and run simulations. Put together a pulse train that is representative of a piece of the expected PWM signal, pass it through the active filter and run a transient analysis. The nice thing about using the simulator is it allows you to change things such as the filter cutoff and the assess the performance.

    If you don't have a PSpice simulator, TI has a free one, TINA-TI, that can be downloaded from the TI website. It is very easy to learn, intuitive and most first time users are up and running with it in about 15 to 20 minutes.

    The ability to resolve a signal down to 16 bits will come down to the op amp that is selected. Noise is one consideration, and it looks like speed is going to be another. You can use an ideal op model to determine if this is a doable approach. Then if so, a search for the best amplifier option would come next.

    Regards, Thomas

    PA - Linear Applications Engineering