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INA220 Intermittent Errors when measuring 0mA

Other Parts Discussed in Thread: INA220

We have a board that uses 5 x INA220 devices and an I2C EEPROM on the same bus. The I2C bus is controlled from an FPGA and runs at 400kHz.

The config register of the  INA220 devices are all as per the default setting in the datasheet (continuous bus & shunt conv, 12-bit 532 us, 40mV PGA). The calibration register is set to 8192 (to give current result in 1mA per bit from a 5mOhm sense resistor) 

We have a problem that we first noticed with the INA220 device attached to our unused "expansion" 12V rail that measures 12V BUT zero current (since it is currently unused). We expect to read zero or very close to zero current and/or shunt voltage, BUT, occasionally we get a spurious reading from the shunt voltage register, the current register or both. The spurious reading is very often around 2306,2304,2558, and sometimes around the negative of these values, but can sometimes also be a very high or very low (negative) reading (+32000 ish or -32000 ish)

One of the other INA220 devices is on a 5V0 rail and usually measures a positive current (without issue). The design has the recommended RCR filter so as an experiment we removed one of the filter R's and shorted out the sense resistor to simulate zero current. We saw a similar effect. ie occasional spurious readings.

We have done many experiments to narrow down the problem. We have scoped the I2C signals with a high speed scope and can see no issues with regard to signal integrity.

We now have an experimental setup as follows :-

One single INA220 device (powered from 3V3 and measuring a 12V rail) on the I2C bus from the FPGA (all other I2C devices physically removed from the PCB).

FPGA code resets the INA220, then sets the config and calibration registers (as noted above), and then continually loops just reading the bus voltage, shunt voltage, and current registers in this sequence. The FPGA code records the max and min values for each and every one of these 3 parameters that we read back over I2C.

The FPGA monitors the I2C bus SDA & SCL lines and checks that they are the expected value after every transition if possible (ie when under the control of the FPGA) and checks for the ACK bit. We see no I2C related protocol issues or errors.

We NEVER see an issue with the bus voltage value. The bus voltage max & min values are always within a few mV of the expected 12V value.

If we add a small positive current load (10mA ish), OR, small negative current load (-10mA ish) using a resistor then we can leave the unit running for many hours (around 8-10 hours overnight) and not see an issue and the max & min recordings are within a few mA of the expected +10mA or -10mA. AND, as per our cal reg setting of 8192, and as expected, we always see the current reg max/min being double the shunt voltage max/min value.

However, if we have no current load, and the readings hover around zero (just above and just below zero) then we see issues with spurious readings. Usually it only takes a few seconds or minutes to get a spurious reading but sometimes this does take longer. 

Interestingly the readings from the shunt voltage register and the current register do not seem to correlate in this 'spurious reading' situation. With our cal reg value of 8192 we would expect the max current reg value to be DOUBLE the shunt voltage reg value, but we have had situations where we see a spurious max/min reading from the shunt voltage reg, but nothing spurious from the current reg, or, we see a spurious max/min from the current reg, but nothing spurious from the shunt voltage reg, or we see spurious max/min readings from BOTH the shunt voltage reg AND the current reg, BUT both of them being in the same sort of range. eg a shunt max value in the region of 2300 and a current max value in the region of 2500, BUT the current max value is NOT double the shunt value. 

We have also tried changing the config reg to change the ADC averaging of the shunt voltage to average 2 samples (SADC mode of B"1001") but this seems to have no effect. ie the most common spurious reading remains in the region of 2300 to 2500. If only one of the two samples was a spurious value and the other was close to zero as expected, then we would expect  the 2 sample average to be half of the 2300 to 2500 range, but this does not appear to change. This suggests the issue is not with the ADC measurement, but more with the processing of the value and reporting it over I2C.

Our design monitors the currents and voltage to provide over-current and over-voltage 'trips' so these spurious readings cause occasional 'trips' and this is causing us issues.

We are convinced the INA220 has an internal issue when measuring currents around zero. Is this a known issue and are there any fixes?

Thanks

 

  • Hi Tony,

    I received your question. Allow me some time for review all the details.

    Regards
  • May I commend you upon your creation of a highly and skillfully prepared post?  Excellent effort.

    That said - upon how many boards does this issue manifest?   Single board anomalies are the bane of all diagnostic groups - suspect this one no different.  (I've read your post twice - searching for (some) percentage of occurrence - your issue - none revealed...)

    Your method of, "Changing the ADC averaging to 2 samples" seems inspired - yet cannot you repeat this test over a larger number of samples?  Your identification of, "internal device processing vs. device measurement" reveals great insight - bravo!   Best to further "beat that path" - I'd suggest.   (and do so upon multiple boards - seeking consistency of response.  

    In the event that "device processing" is suspect (as it appears) should not you, "dial down" your (400KHz) I2C speed - to remove (speed) from the issue inventory?   Firm/I "lean to that" as high likelihood...

    You need adequate "ammo" so that vendor "pros" can "build your case."   Many, many "false alarms" occur here/elsewhere - factual "building & selling" your case ALWAYS helps!

    Might your board be subject to RF, EMI, or RFI?   Or some nearby noise event - or even ESD?   (is it possible that charge builds upon the undriven device inputs - and that yields your issue?)

    You report (reasonable) success at/around ±10mA - would not further (and lowered level) testing prove worthwhile?   Possibly your identification of some (exact) "minimum current level" to reduce/eliminate your issue will prove useful to vendor staff.   And - does this not suggest a "work-around" (i.e.  your provisioning of this "known & minimal" current flow) as opposed to allowing 0mA?

    Again - great job...

  • Thank you for your kind complements ref the post. My colleagues and I have many decades of design experience in the industry, particularly in test, and have found issues in several 'mature' chips before now. I guess this is what showed through.

    Firstly I saw the 10USD bet 'tag' on this being a 400kHz I2C issue.... well no it is almost certainly not..... Whilst writing the earlier post we were running another test with the I2C bus running 10x slower at 40kHz. This included all the timing parameters (eg bus free time, hold times repeated start setup etc not just the raw SCL freq) Admittedly the edge rates will be the same but the raw "frequency" and setup/hold times all being 10x slower had no real effect.... we still saw the spurious readings although it seemed (subjective) to take longer to catch one. However this would not seem unreasonable since the retrieval of data from the device was 10x slower, and as per the previous post the speculation is that the conversion process is OK but that the data processing / I2C area is the issue.
    With regard to the edge rates... well the rising edges of I2C are slow due to the passive pull-ups so only the falling edges could/should be of concern, BUT, if edge rate was an issue (possibly due to capacitive coupling inside the chip somewhere) then why is the effect ONLY seen on the shunt/current readings and NOT on the bus voltage reading, and why would it not happen on all currents and not just around zero? I find it highly unlikely that I2C speed or edge rate is an issue.

    At one point we did wonder if the chip addressing was an issue since the main INA220 device in question is the one on the 12V bus and has A0=Gnd and A1=SDA). This is partly why we did the experiment on the chip on the 5V0 bus (A0=3V3, A1=Gnd). We still saw issues so ruled this out along with the effect being related to bus voltage.

    To your other points/suggestions:

    To eliminate the rogue board theory, we had already looked for the issue on 3 other boards (so 4 in total), and saw the same effect on all of them. Appologies for not being clear before. I would also note we've seen it on more than one chip on a board also (note the experiment on the chip on the 5V0 bus).

    The +/-10mA was a bit of an approximation. It was actually around 4-6mA positive and negative ie around 2-3 bits of shunt voltage reading.
    This was about as low a current as we could go to guarantee a continuous positive or continuous negative value (as far as we could tell/measure it).
    A 'positive' run overnight (12 hours ish) recorded shunt voltage min/max of 0bits / 3bits ie 0mA / 6mA.
    A 'negative' run overnight (12 hours ish) recorded shunt voltage min/max of -5bits / -2bits ie -10mA / -4mA.
    The min/max bus voltage on both the above runs was 12.028/12.040 ie 12mV variation which is only a p-p span of 3 bits with the 4mV resolution.

    We are working in an ESD safe environment so no concerns there and see it on multiple chips/boards.
    There can be no "charge build-up" on the unused device as you put it.... the 12V bus is an intermediate rail that supplies 5V, 3v3, and 2V5 PSUs that do take current. The 12V is also supplied to an "expansion" connector and it is this 12V feed to this connector which has the 12V INA220 on it.

    With regard to EMI / RFI etc... IF this were a problem, why would this ONLY cause an issue when current hovers around zero, and NEVER (based on experience so far) when within a whisker of zero current but without changing sign? And why is the voltage never affected? Cannot imagine EMI / RFI is the issue, especially with the filtering effect of a sigma-delta converter.

    We may experiment with more averaging at some point, and may also experiment with triggered vs continuous conversions at some point, but will wait for TI to chew on this and respond first before spending more time. Triggered stuff is also more of a pain to implement and the chip spec does say " the data from the last conversion can be read at any time" so it should work just fine in continuous mode.

    I would put money on it being a "zero crossing"  related error to do with the maths etc and/or processing/reporting of the two's complement result.
    I would not be surprised if the ADC result is not properly buffered and held whilst doing the maths and/or supplying the 2 byte result to I2C.
    eg. If an I2C request comes in just before a new conversion result is ready, and if the previous conversion was positive and the new one is negative then maybe there is some mixing-up of old/new data due to the byte-wide nature of I2C and the greater than byte wide result from the ADC (>=12-bit?) and the multiply by cal & divide by 4096 processes.

    I actually think the maths bit may be OK because we see spurious results on the 'raw' shunt voltage as well as the calibrated 'current' register value.

    Fingers crossed that TI can replicate easily enough..... we can!

    Thanks for the input and best regards.

  • Hi Tony,

    Can you please share your email address? I would like to contact you via email for this issue. 

    Regards,

  • Hi Mayrim,

    Sure my email address is [removed for privacy].

    Tony

  • Thank you - and indeed your experience (and interest) still register.

    Firm/I find it most (unfortunate) that vendor retreats into (private-only) (i.e. "hidden solution" and/or analysis.)    Surely you (Tony) deserve to be satisfied - but how does that (singular) solution serve the (far larger) forum group here - drawn to this post?    And if "Private Only" feedback is to be the (ONLY) form supplied - what is the point of this forum?   Of any forum?

    And - is it guaranteed that methods & discoveries (i.e. solutions) made & released here (this thread) will have "Zero Cross-Over Benefit" to other - related products/projects - this forum?   Loss of such related issue resolution disturbs - "Hiding" the solution/work-around serves, "What purpose?"

    It is - beyond any doubt - a severe disservice to (all forum users) to have the analysis & (possible) solution, "Held Hostage." 

    While disappointing many here - might this (privacy movement - so "un-forum like") work against this vendor?    Indeed - while vendor staff are well trained - their experience, tech keenness & business record may not (always) trump those of the larger forum public!   Thus - such, "holding secret" may delay - even prevent - the quickest (and best) shared/communal solution!    Has this (even) been considered - at all - really?

    Poster Tony deserves response - yet (he too) may be victimized when another's question/issue is resolved (secretly) - as appears the case here.

    No one expects full openness, transparency (my own, earlier post) - suffered from that lack.   Yet - if there is a device "hiccup" - is "burying that weakness" more important than Vendor Transparency - and "Open Admission?"    Lack of (some) transparency and "broadcast response" may be a (greater) sin than an (unplanned) device miscue...